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    Structure and method to form input/output devices
    1.
    发明授权
    Structure and method to form input/output devices 有权
    结构和方法来形成输入/输出设备

    公开(公告)号：US08836037B2

    公开(公告)日：2014-09-16

    申请号：US13584156

    申请日：2012-08-13

    申请人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

    发明人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

    IPC分类号： H01L29/78 ,  H01L21/314 ,  H01L27/088

    CPC分类号： H01L21/28185 ,  H01L21/02181 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

    摘要： A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

    摘要翻译： 有限数量的Hi-K材料的原子层沉积（ALD）循环，然后沉积层间电介质并施加另外的Hi-K材料并且可选但优选的退火提供了增加的Hi-K材料含量和增加的输入的击穿电压 与输入/输出（I / O）晶体管相比，与同一芯片或晶圆上形成的逻辑晶体管相比，同时提供I / O和逻辑晶体管的反型层的可扩展性，而不会明显地影响性能或偏置温度不稳定性（BTI）参数。

    STRUCTURE AND METHOD TO FORM INPUT/OUTPUT DEVICES
    2.
    发明申请
    STRUCTURE AND METHOD TO FORM INPUT/OUTPUT DEVICES 有权
    用于形成输入/输出设备的结构和方法

    公开(公告)号：US20140042546A1

    公开(公告)日：2014-02-13

    申请号：US13584156

    申请日：2012-08-13

    申请人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

    发明人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

    IPC分类号： H01L29/78 ,  H01L21/314 ,  H01L27/088

    CPC分类号： H01L21/28185 ,  H01L21/02181 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

    摘要： A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

    摘要翻译： 有限数量的Hi-K材料的原子层沉积（ALD）循环，然后沉积层间电介质并施加另外的Hi-K材料并且可选但优选的退火提供了增加的Hi-K材料含量和增加的输入的击穿电压 与输入/输出（I / O）晶体管相比，与同一芯片或晶圆上形成的逻辑晶体管相比，同时提供I / O和逻辑晶体管的反型层的可扩展性，而不会明显地影响性能或偏置温度不稳定性（BTI）参数。

    Metal gate CMOS with at least a single gate metal and dual gate dielectrics
    8.
    发明授权
    Metal gate CMOS with at least a single gate metal and dual gate dielectrics 有权
    具有至少一个栅极金属和双栅极电介质的金属栅极CMOS

    公开(公告)号：US07709902B2

    公开(公告)日：2010-05-04

    申请号：US12211647

    申请日：2008-09-16

    申请人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

    发明人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

    IPC分类号： H01L31/119

    CPC分类号： H01L21/823857 ,  H01L21/823878 ,  H01L21/84

    摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.

    摘要翻译： 提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。 根据本发明，nFET和pFET都包括至少一个栅极金属，并且nFET栅极堆叠被设计成具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质 堆没有净正电荷。 特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。 在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质 。

    METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS
    10.
    发明申请
    METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS 有权
    金属门CMOS至少具有单栅极金属和双栅电极

    公开(公告)号：US20090011552A1

    公开(公告)日：2009-01-08

    申请号：US12210703

    申请日：2008-09-15

    申请人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

    发明人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823878 ,  H01L21/84

    摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.

    摘要翻译： 提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。 根据本发明，nFET和pFET都包括至少单个栅极金属，并且nFET栅极堆叠被设计为具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质 堆没有净正电荷。 特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。 在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质 。