公开(公告)号：US20250079337A1

公开(公告)日：2025-03-06

申请号：US18460863

申请日：2023-09-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jonghae Kim ,  Bin Yang ,  Giridhar Nallapati

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

Abstract: An integrated circuit (IC) includes a plurality of first metallization layers on a front side of a circuit layer and a plurality of second metallization layers on a back side of the circuit layer. A semiconductor substrate on the back side of the circuit layer of the IC is thinned to improve access to devices from the back side. The plurality of second metallization layers are employed to provide increased interconnection among the devices without increasing area and may provide increased access to external contacts. Thinning the semiconductor substrate reduces structural rigidity needed for processing, so the IC also includes a stiffening layer on one of the plurality of first metallization layers and the plurality of second metallization layers to increase rigidity and first vias extending through the stiffening layer to couple to first contacts.

公开(公告)号：US11973020B2

公开(公告)日：2024-04-30

申请号：US17470274

申请日：2021-09-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Lixin Ge ,  Giridhar Nallapati

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76838 ,  H01L28/40

Abstract: Disclosed are examples of a device and method of fabricating a device including a first top contact, a second top contact, adjacent the first top contact, a first mesa disposed below the first top contact and a second mesa disposed below the second top contact. A first plate of a metal-insulator-metal (MIM) capacitor is disposed below the first top contact and electrically coupled to the first top contact. A first insulator of the MIM capacitor is disposed on the first plate. A second plate of the MIM capacitor is disposed on the first insulator and electrically coupled to the second top contact. A second insulator of the MIM capacitor is disposed on the second plate. A third plate of the MIM capacitor is disposed on the second insulator and electrically coupled to the first top contact.

公开(公告)号：US20200066630A1

公开(公告)日：2020-02-27

申请号：US16106679

申请日：2018-08-21

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Jie Deng ,  John Zhu ,  Giridhar Nallapati

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L21/8234

Abstract: A semiconductor device includes a contact via and a metal interconnect on the contact via. The metal interconnect has a portion extending in a lengthwise direction that is wrapped around and in contact with a sidewall of the contact via. Along a widthwise direction, the metal interconnect does not contact the sidewall of the contact via.

公开(公告)号：US10418244B2

公开(公告)日：2019-09-17

申请号：US15408796

申请日：2017-01-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L21/033 ,  G03F7/00 ,  H01L21/308 ,  H01L27/118

Abstract: Aspects describing modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area are disclosed. In one aspect, a modified SAQP process includes disposing multiple mandrels. First spacers are disposed on either side of each mandrel, and second spacers are disposed on either side of each first spacer. A cut pattern mask is disposed over the second spacers and includes openings that expose second spacers corresponding to locations in which voltage rails are to be disposed. The voltage rails are formed by removing the second spacers exposed by the openings in the cut pattern mask, and disposing the voltage rails in the corresponding locations left vacant by removing the second spacers. Routing lines are disposed over routing tracks formed between each set of the remaining second spacers to allow for interconnecting of active devices formed in the IC cell.

公开(公告)号：US20190195700A1

公开(公告)日：2019-06-27

申请号：US16268669

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Periannan Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  H01L23/522 ,  H01L23/34 ,  G01K7/18 ,  H01L49/02 ,  G01K7/24 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/66

CPC classification number: G01K7/01 ,  G01K7/186 ,  G01K7/24 ,  H01L21/32139 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0629 ,  H01L28/24

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US20180058943A1

公开(公告)日：2018-03-01

申请号：US15246006

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Chidi Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  H01L21/66 ,  H01L49/02 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  G01K7/24

CPC classification number: G01K7/01 ,  G01K7/186 ,  G01K7/24 ,  H01L21/32139 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0629 ,  H01L28/24

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US20150091060A1

公开(公告)日：2015-04-02

申请号：US14040366

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  PR Chidambaram ,  John Jianhong Zhu ,  Jihong Choi ,  Da Yang ,  Ravi Mahendra Todi ,  Giridhar Nallapati ,  Chock Hing Gan ,  Ming Cai ,  Samit Sengupta

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/778 ,  H01L29/7834

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel

Abstract translation: 在特定实施例中，半导体器件包括源极区和漏极区之间的高迁移率沟道。 高迁移率通道基本上延伸了一个门的长度。 半导体器件还包括从源极区域或漏极区域向高迁移率通道延伸的掺杂区域。 衬底的一部分位于掺杂区域和高迁移率通道之间

公开(公告)号：US12218041B2

公开(公告)日：2025-02-04

申请号：US17237828

申请日：2021-04-22

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L21/48 ,  H01L49/02

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US11973019B2

公开(公告)日：2024-04-30

申请号：US17324614

申请日：2021-05-19

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Stanley Seungchul Song ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L49/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/5223 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L28/40 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16146

Abstract: Deep trench capacitors (DTCs) in an inter-layer medium (ILM) on an interconnect layer of an integrated circuit (IC) die is disclosed. A method of fabricating an IC die comprising DTCs in the ILM is also disclosed. The DTCs are disposed on an IC, in an ILM, to minimize the lengths of the power and ground traces coupling the DTCs to circuits in a semiconductor layer. The DTCs and the semiconductor layer are on opposite sides of the metal layer(s) used to interconnect the circuits, so the locations of the DTCs in the ILM can be independent of circuit layout and interconnect routing. IC dies with DTCs disposed in the ILM can significantly reduce voltage droop and spikes in IC dies in an IC stack. In one example, DTCs are also located in trenches in the substrate of the IC die.

公开(公告)号：US20220344250A1

公开(公告)日：2022-10-27

申请号：US17237828

申请日：2021-04-22

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/48

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.