公开(公告)号：US20150143076A1

公开(公告)日：2015-05-21

申请号：US14082067

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/3887 ,  G06F9/3895 ,  G06F9/3897 ,  G06F15/8053 ,  G06F17/10

Abstract: Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The merging circuitry is configured to merge an output vector data sample set from execution units as a result of performing vector processing operations in-flight while the output vector data sample set is being provided over the output data flow paths from the execution units to the vector data memory to be stored. The merged output vector data sample set is stored in a merged form in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in execution units.

Abstract translation: 公开了在执行单元和向量数据存储器之间的数据流路径中采用合并电路的向量处理引擎（VPE），以提供存储到向量数据存储器中的输出矢量数据的飞行中合并。 还公开了相关向量处理指令，系统和方法。 在VPE中的执行单元和向量数据存储器之间的数据流路径中提供合并电路。 合并电路被配置为作为执行向量处理操作的结果，从执行单元合并输出向量数据样本集合，同时输出向量数据样本集被提供在从执行单元到向量的输出数据流路径上 要存储的数据存储器。 合并的输出向量数据样本集以合并形式存储在向量数据存储器中，而不需要额外的后处理步骤，这可能会延迟在执行单元中执行的后续向量处理操作。

公开(公告)号：US09977676B2

公开(公告)日：2018-05-22

申请号：US14082081

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Fahad Ali Mujahid

IPC: G06F9/30 ,  G06F7/76 ,  G06F15/80 ,  G06F9/38

CPC classification number: G06F9/30181 ,  G06F7/76 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8053

Abstract: Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The reordering circuitry is configured to reorder output vector data sample sets from execution units as a result of performing vector processing operations in-flight while the output vector data sample sets are being provided over the data flow paths from the execution units to the vector data memory to be stored. In this manner, the output vector data sample sets are stored in the reordered format in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in the execution units.

公开(公告)号：US09792118B2

公开(公告)日：2017-10-17

申请号：US14082075

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Fahad Ali Mujahid ,  Afshin Shiravi

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/3887 ,  G06F9/3895 ,  G06F15/8053

Abstract: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption are disclosed. Related vector processor systems and methods are also disclosed. The VPEs are configured to provide filter vector processing operations. To minimize re-fetching of input vector data samples from memory to reduce power consumption, a tapped-delay line(s) is included in the data flow paths between a vector data file and execution units in the VPE. The tapped-delay line(s) is configured to receive and provide input vector data sample sets to execution units for performing filter vector processing operations. The tapped-delay line(s) is also configured to shift the input vector data sample set for filter delay taps and provide the shifted input vector data sample set to execution units, so the shifted input vector data sample set does not have to be re-fetched during filter vector processing operations.

公开(公告)号：US09684509B2

公开(公告)日：2017-06-20

申请号：US14082073

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F9/30 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8053

Abstract: Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The merging circuitry is configured to merge an output vector data sample set from execution units as a result of performing vector processing operations in-flight while the output vector data sample set is being provided over the output data flow paths from the execution units to the vector data memory to be stored. The merged output vector data sample set is stored in a merged form in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in execution units.

公开(公告)号：US20170083441A1

公开(公告)日：2017-03-23

申请号：US15080439

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Scott Wang-Yip Cheng ,  Raheel Khan ,  Warren Lew

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0646 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/601 ,  G06F2212/602 ,  G06F2212/621

Abstract: Apparatuses and techniques are disclosed herein that enable region-based cache management. In some aspects, a configuration for a region of cache memory is determined based on characteristics of information to be written to the cache memory. Based on the determined configuration, an address range of the cache memory is allocated to define the region within the cache memory. A cache policy is the applied to the allocated address range to control caching of the information written to the region of cache memory. By so doing, regions of cache memory and respective caching policies applied thereto can be optimized for a variety of information types or usages.

公开(公告)号：US20150234449A1

公开(公告)日：2015-08-20

申请号：US14181122

申请日：2014-02-14

Applicant: QUALCOMM INCORPORATED

Inventor： Raheel Khan ,  Paul Donald Krivacek

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3243 ,  G06F1/329 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24

Abstract: Techniques for fast power gating of vector processors are described herein. In one embodiment, a method for power gating a vector processor comprises powering up a vector unit from an inactive state at approximately a boundary of a transmission time interval, and powering down the vector unit within the transmission time interval after the vector unit completes a task within the transmission time interval.

Abstract translation: 本文描述了用于矢量处理器的快速功率门控的技术。 在一个实施例中，用于向量处理器的电源门控的方法包括在传输时间间隔的大约边界的非活动状态下对向量单元进行加电，以及在向量单元完成任务之后的传输时间间隔内对向量单元进行掉电 在传输时间间隔内。

公开(公告)号：US20150143085A1

公开(公告)日：2015-05-21

申请号：US14082081

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Fahad Ali Mujahid

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F7/76 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8053

Abstract: Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The reordering circuitry is configured to reorder output vector data sample sets from execution units as a result of performing vector processing operations in-flight while the output vector data sample sets are being provided over the data flow paths from the execution units to the vector data memory to be stored. In this manner, the output vector data sample sets are stored in the reordered format in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in the execution units.

Abstract translation: 公开了在执行单元和向量数据存储器之间的数据流路径中使用重排序电路的向量处理引擎（VPE），以提供存储到向量数据存储器中的输出矢量数据的飞行中排序。 还公开了相关矢量处理器系统和方法。 在VPE中的执行单元和向量数据存储器之间的数据流路径中提供重排序电路。 重新排序电路被配置为作为执行向量处理操作的结果，在执行单元中重新排序输出向量数据样本集，同时输出向量数据样本集被提供在从执行单元到向量数据存储器的数据流路径上 被存储。 以这种方式，输出矢量数据样本集以重新排序的格式存储在矢量数据存储器中，而不需要额外的后处理步骤，这可能会延迟在执行单元中执行的后续矢量处理操作。

公开(公告)号：US20150143078A1

公开(公告)日：2015-05-21

申请号：US14082075

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Fahad Ali Mujahid ,  Afshin Shiravi

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/3887 ,  G06F9/3895 ,  G06F15/8053

Abstract: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption are disclosed. Related vector processor systems and methods are also disclosed. The VPEs are configured to provide filter vector processing operations. To minimize re-fetching of input vector data samples from memory to reduce power consumption, a tapped-delay line(s) is included in the data flow paths between a vector data file and execution units in the VPE. The tapped-delay line(s) is configured to receive and provide input vector data sample sets to execution units for performing filter vector processing operations. The tapped-delay line(s) is also configured to shift the input vector data sample set for filter delay taps and provide the shifted input vector data sample set to execution units, so the shifted input vector data sample set does not have to be re-fetched during filter vector processing operations.

Abstract translation: 公开了采用抽头延迟线的矢量处理引擎（VPE），用于提供具有减少的采样重新获取和功耗的精确滤波器矢量处理操作。 还公开了相关矢量处理器系统和方法。 VPE被配置为提供滤波器向量处理操作。 为了最小化来自存储器的输入矢量数据样本的重新获取以降低功耗，在矢量数据文件和VPE中的执行单元之间的数据流路径中包括抽头延迟线。 抽头延迟线被配置为接收输入矢量数据样本集并将其提供给用于执行滤波器向量处理操作的执行单元。 抽头延迟线还被配置为移位用于滤波器延迟抽头的输入矢量数据样本集，并将移位的输入矢量数据样本集合提供给执行单元，因此移位的输入向量数据样本集不必是re 在滤波器矢量处理操作期间。

公开(公告)号：US10061581B2

公开(公告)日：2018-08-28

申请号：US14170193

申请日：2014-01-31

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Jun Ho Bahn ,  Vijay Bantval

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3875

Abstract: Systems and methods for performing on-the-fly format conversion on data vectors during load/store operations are described herein. In one embodiment, a method for loading a data vector from a memory into a vector unit comprises reading a plurality of samples from the memory, wherein the plurality of samples are packed in the memory. The method also comprises unpacking the samples to obtain a plurality of unpacked samples, performing format conversion on the unpacked samples in parallel, and sending at least a portion of the format-converted samples to the vector unit.

公开(公告)号：US09996439B2

公开(公告)日：2018-06-12

申请号：US15080450

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Scott Wang-Yip Cheng ,  Raheel Khan ,  Kanwal Banga

IPC: G06F11/00 ,  G06F11/26 ,  G06F11/263 ,  G06F11/27 ,  H04L1/24

CPC classification number: G06F11/261 ,  G06F11/263 ,  G06F11/27 ,  H04L1/241

Abstract: Various aspects describe an on-chip, hardware error-generator component. In some cases, the hardware error-generator component connects to a data path between two components contained within a same chip. Upon receiving an error simulation input, the hardware error-generator component modifies data being transmitted on the data path by inserting a data pattern that simulates an error condition. Alternately or additionally, the hardware error-generator randomly alters one or more of the transmitted data bits.