公开(公告)号：US20210134812A1

公开(公告)日：2021-05-06

申请号：US16669837

申请日：2019-10-31

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Haining YANG ,  Bin YANG

IPC: H01L27/1159 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a ferroelectric (FE) semiconductor device having a channel region; a gate oxide; a FE region, wherein the gate oxide is disposed between the FE region and the channel region; a gate region, wherein the FE region is disposed between the gate oxide and the gate region; a first semiconductor region disposed adjacent to the channel region; and a second semiconductor region disposed adjacent to the channel region. The semiconductor device may also include a transistor, wherein a region of the transistor is connected to the gate region, the first semiconductor region, or the second semiconductor region of the FE semiconductor device.

公开(公告)号：US20200020795A1

公开(公告)日：2020-01-16

申请号：US16033597

申请日：2018-07-12

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Haining YANG ,  Hyeokjin LIM

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/321

Abstract: A semiconductor device includes a substrate, a gate region formed on the substrate, a self-aligned gate cut formed in the gate region, and a middle of line (MOL) area formed on the gate region, wherein the self-aligned gate cut provides critical dimensions in a range from 5 nm to 30 nm. The self-aligned gate cut reduces capacitance and power, provides flexibility in placement of the MOL area, and reduces local routing congestion.

公开(公告)号：US20180076139A1

公开(公告)日：2018-03-15

申请号：US15352342

申请日：2016-11-15

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang LIU ,  Haining YANG ,  Youseok SUH ,  Jihong CHOI ,  Junjing BAO

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.

公开(公告)号：US20160284836A1

公开(公告)日：2016-09-29

申请号：US14668476

申请日：2015-03-25

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang LIU ,  Haining YANG

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.

Abstract translation: 集成逻辑电路中的n型至p型鳍FET强度比可以通过在有源和虚拟栅电极中使用切割区来调节。 在一些示例中，虚拟栅电极和有源栅电极的单独切割区域可以用于允许不同长度的栅极通过有源区域，从而导致适当调谐的集成逻辑电路。

公开(公告)号：US20240321965A1

公开(公告)日：2024-09-26

申请号：US18189442

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Xia LI ,  Chih-Sung YANG ,  Kwanyong LIM ,  Ming-Huei LIN ,  Hyunwoo PARK ,  Haining YANG

IPC: H01L29/08 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/76841 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/6656

Abstract: Disclosed are devices that include a contact for electrical connection with a source/drain. The contact occupies a full width of a contact well other than areas occupied by sidewall spacers. As a result, high resistivity (due to the presence of liners and nucleation layers within the contact well in conventional devices) is reduced or eliminated.

公开(公告)号：US20240266217A1

公开(公告)日：2024-08-08

申请号：US18166403

申请日：2023-02-08

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Haining YANG ,  Hyunwoo PARK ,  Kwanyong LIM ,  Ming-Huei LIN

IPC: H01L21/768 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/3212 ,  H01L29/66545 ,  H01L29/6656

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate structure disposed on a substrate, a gate spacer adjacent to the gate structure, a source/drain structure adjacent to the gate spacer, a first dielectric layer disposed on the substrate and the source/drain structure, an etch stop spacer over the first dielectric layer and adjacent to the gate spacer, and an etch stop layer over the gate structure, the gate spacer, and the etch stop spacer. The semiconductor structure further includes a source/drain contact extending through the etch stop layer and the first dielectric layer and in contact with the source/drain structure, a sidewall of the source/drain contact adjoining a sidewall of the etch stop layer and a sidewall of the etch stop spacer.

公开(公告)号：US20240105728A1

公开(公告)日：2024-03-28

申请号：US18472074

申请日：2023-09-21

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Haining YANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN ,  Jun YUAN ,  Giridhar NALLAPATI ,  Deepak SHARMA

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Disclosed are standard cells, transistors, and methods for fabricating the same. In an aspect, a transistor includes a drain and a source each including a first drain/source silicide layer on a frontside surface of the drain/source and a second drain/source silicide layer on a backside surface of the drain/source. The first drain silicide layer is coupled to a first drain contact structure or the second drain silicide layer is coupled to a second drain contact structure. The first source silicide layer is coupled to a first source contact structure or the second source silicide layer is coupled to a second source contact structure. A gate structure is disposed between the source and the drain. A channel is at least partially enclosed by the gate structure and disposed between the source and the drain and is recessed from the backside surfaces of the source and drain.

公开(公告)号：US20240096698A1

公开(公告)日：2024-03-21

申请号：US17933683

申请日：2022-09-20

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Chih-Sung YANG ,  Haining YANG

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76879 ,  H01L27/10855

Abstract: In an aspect, a transistor comprises a gate structure having a metal gate, a dielectric layer at least partially surrounding the metal gate, a metal cap over a portion of the metal gate that is not surrounded by the dielectric layer, and a gate contact comprising tungsten in direct contact with the metal cap. In another aspect, a transistor comprises source, drain, and channel regions, a gate structure comprising a metal gate between gate spacers above the channel region, and a source or drain (S/D) contact structure. The S/D contact structure comprises an S/D barrier layer above at least a portion of the source or drain region and in direct contact with a gate spacer, and an S/D contact, comprising a first portion above the S/D barrier layer; and a second portion comprising tungsten, above the first portion.

公开(公告)号：US20220352347A1

公开(公告)日：2022-11-03

申请号：US17245695

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Haining YANG ,  Youseok SUH

IPC: H01L29/66 ,  H01L23/535 ,  H01L29/417 ,  H01L21/02 ,  H01L21/768

Abstract: In some aspects, a semiconductor die includes an insulation layer disposed on a substrate, a gate spacer disposed in the insulation layer, a gate disposed between the gate spacer, a first dielectric gate layer disposed on the gate between the gate spacer, a second dielectric gate layer disposed on the first dielectric gate layer between the gate spacer, a gate contact coupled to the gate and in contact with the first dielectric gate layer and the second dielectric gate layer, and a source/drain contact that has a single inner spacer.

公开(公告)号：US20220336608A1

公开(公告)日：2022-10-20

申请号：US17231284

申请日：2021-04-15

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Junjing BAO

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/40 ,  H01L21/8238

Abstract: In an aspect, a semiconductor device includes a gate. The gate includes a first portion that is located on one end of the gate, a second portion that is located on an opposite end of the gate from the first portion, and a third portion that is located in-between the first portion and the second portion. A first cap located on top of the first portion. A second cap located on top of the second portion. The third portion is capless. A gate contact is located on top of the third portion.