公开(公告)号：US20150170736A1

公开(公告)日：2015-06-18

申请号：US14106575

申请日：2013-12-13

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Ashish Akhilesh ,  Venkatasubramanian Narayanan

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C7/12

Abstract: A memory device biasing circuit is disclosed, the circuit having a pair of semiconductor devices coupled to receive a supply voltage having a supply voltage level suitable for operating a memory device in an active mode and operable for providing an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the memory device in a data retention mode. The pair of semiconductor devices includes a first semiconductor device; and, a second semiconductor device that includes an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices includes each of an N-type semiconductor device and a P-type semiconductor device. The memory device biasing circuit further includes a bias adjustment circuit coupled to the second semiconductor device and configured to adjust the operation of the second semiconductor device based on the supply voltage.

Abstract translation: 公开了一种存储器件偏置电路，该电路具有一对半导体器件，其被耦合以接收电源电压，该电源电压具有适于在有源模式下操作存储器件的电源电压电平，并可操作以向存储器件提供可调节的偏置电压， 大于在数据保持模式下操作存储器件的最小电压电平。 所述一对半导体器件包括第一半导体器件; 以及包括与第一半导体器件相反的半导体器件的第二半导体器件，使得该对半导体器件包括N型半导体器件和P型半导体器件中的每一个。 存储器件偏置电路还包括耦合到第二半导体器件并被配置为基于电源电压来调整第二半导体器件的操作的偏置调整电路。

公开(公告)号：US10103626B1

公开(公告)日：2018-10-16

申请号：US15647326

申请日：2017-07-12

Applicant: QUALCOMM Incorporated

Inventor： Venkatasubramanian Narayanan ,  Dorav Kumar ,  Ramaprasath Vilangudipitchai ,  Venugopal Boynapalli

IPC: H02M3/157 ,  H03K17/687 ,  H03K19/173 ,  H02M3/335

Abstract: A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.

公开(公告)号：US09979394B2

公开(公告)日：2018-05-22

申请号：US15044988

申请日：2016-02-16

Applicant: QUALCOMM Incorporated

Inventor： Qi Ye ,  Animesh Datta ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli

IPC: H03K3/356 ,  H03K19/003 ,  H03K3/037 ,  H03K3/033 ,  H03K5/04

CPC classification number: H03K19/00384 ,  H03K3/033 ,  H03K3/0375 ,  H03K5/04

Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

公开(公告)号：US09852859B2

公开(公告)日：2017-12-26

申请号：US14981183

申请日：2015-12-28

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Dorav Kumar ,  Bilal Zafar ,  Ramaprasath Vilangudipitchai ,  Venkatasubramanian Narayanan ,  Xi Luo

IPC: H01H47/00 ,  H03K19/00

CPC classification number: H01H47/00 ,  H03K19/0008

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.

公开(公告)号：US20170186576A1

公开(公告)日：2017-06-29

申请号：US14981183

申请日：2015-12-28

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Dorav Kumar ,  Bilal Zafar ,  Ramaprasath Vilangudipitchai ,  Venkatasubramanian Narayanan ,  Xi Luo

IPC: H01H47/00

CPC classification number: H01H47/00 ,  H03K19/0008

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.

公开(公告)号：US09330785B1

公开(公告)日：2016-05-03

申请号：US14698844

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Venkatasubramanian Narayanan ,  Keith Alan Bowman ,  Alex Dongkyu Park ,  Francois Ibrahim Atallah

IPC: G11C11/00 ,  G11C29/12 ,  G11C11/419

CPC classification number: G11C11/417 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50

Abstract: In a static random access memory (SRAM), such as an SRAM cache in a processor or system-on-a-chip (SoC) device, an aging sensor is provided for testing degradation of SRAM cells comprising p-channel metal oxide semiconductor (PMOS) transistors. The minimum power supply voltage VDDMIN for the SRAM may be dynamically scaled up as the SRAM ages by performing read tests with and without the wordline overdrive voltage VWLOD.

Abstract translation: 在诸如处理器或片上系统（SoC）装置中的SRAM缓存的静态随机存取存储器（SRAM）中，提供了老化传感器，用于测试包含p沟道金属氧化物半导体的SRAM单元的劣化 PMOS）晶体管。 SRAM的最小电源电压VDDMIN可以通过执行具有和不具有字线过驱动电压VWLOD的读取测试随SRAM而老化。