公开(公告)号：US20200176562A1

公开(公告)日：2020-06-04

申请号：US16781820

申请日：2020-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532

Abstract: In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.

公开(公告)号：US20170365657A1

公开(公告)日：2017-12-21

申请号：US15186326

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Hyeokjin Bruce LIM ,  Satyanarayana SAHU ,  Venugopal BOYNAPALLI

IPC: H01L29/06 ,  H01L27/02 ,  H01L23/535

CPC classification number: H01L29/0646 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.

公开(公告)号：US20240322819A1

公开(公告)日：2024-09-26

申请号：US18188656

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Ramaprasath VILANGUDIPITCHAI ,  Pavan Kumar PATIBANDA ,  Joshua ONG ,  Chethan SWAMYNATHAN ,  Vajram GHANTASALA ,  Venugopal BOYNAPALLI ,  Madan KRISHNAPPA ,  Vineet OORAMKUMARATH ,  Mohamed Saud MUSLIYARAKATH

IPC: H03K17/687 ,  H03K3/012 ,  H03K3/3562

CPC classification number: H03K17/6872 ,  H03K3/012 ,  H03K3/35625

Abstract: Aspects of the present disclosure provide cells including integrated switches and/or integrated clamps. In some aspects, a cell includes a circuit having an input and an output, and a switch coupled between a supply rail and the circuit, wherein the switch is configured to receive an enable signal, turn on when the enable signal has a first logic value, and turn off when the enable signal has a second logic value. The cell also includes a first clamp coupled to the output of the circuit, wherein the first clamp is configured to clamp the output of the circuit when the enable signal has the second logic value.

公开(公告)号：US20210280571A1

公开(公告)日：2021-09-09

申请号：US16808336

申请日：2020-03-03

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin LIM ,  Bharani CHAVA ,  Foua VANG ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: H01L27/02 ,  H01L23/528 ,  H03K19/0185

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2≤m m*P

公开(公告)号：US20200176563A1

公开(公告)日：2020-06-04

申请号：US16781856

申请日：2020-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532

Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

公开(公告)号：US20170287933A1

公开(公告)日：2017-10-05

申请号：US15264560

申请日：2016-09-13

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Satyanarayana SAHU ,  Hyeokjin LIM ,  Mukul GUPTA

IPC: H01L27/118 ,  H01L29/06

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L29/0642 ,  H01L29/0649 ,  H01L2027/11829 ,  H01L2027/11866

Abstract: A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.

公开(公告)号：US20170257080A1

公开(公告)日：2017-09-07

申请号：US15061055

申请日：2016-03-04

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI

IPC: H03K3/012 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356104 ,  H03K3/35625

Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

公开(公告)号：US20220093594A1

公开(公告)日：2022-03-24

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Deepak SHARMA ,  Bharani CHAVA ,  Hyeokjin LIM ,  Peijie FENG ,  Seung Hyuk KANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Kern RIM ,  Giridhar NALLAPATI ,  Venugopal BOYNAPALLI ,  Foua VANG

IPC: H01L27/095 ,  H03K19/0185 ,  H01L23/528 ,  H01L29/78

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20200335151A1

公开(公告)日：2020-10-22

申请号：US16849616

申请日：2020-04-15

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Keejong KIM ,  Changho JUNG ,  Venugopal BOYNAPALLI

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-transfer transistor conducts during a charge-transfer period. Prior to the charge-transfer period, a bitcell is coupled to the bit line to drive a bitcell-effected voltage on to the bit line. The charge-transfer driver drives the gate voltage such that the charge-transfer transistor only conducts when the bitcell-effected voltage equals a pre-charge voltage for the bit line.

公开(公告)号：US20200266821A1

公开(公告)日：2020-08-20

申请号：US15929520

申请日：2020-05-07

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana SAHU ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM ,  Mickael MALABRY ,  Mukul GUPTA

IPC: H03K19/0948 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.