公开(公告)号：US20150324309A1

公开(公告)日：2015-11-12

申请号：US14806788

申请日：2015-07-23

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Vlad Fruchter ,  Lawrence Lai ,  Pradeep Batra ,  Steven C. Woo ,  Wayne Frederick Ellis

IPC: G06F13/28 ,  G11C7/10 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0671 ,  G06F12/06 ,  G06F13/16 ,  G06F13/1621 ,  G06F13/1626 ,  G06F13/1668 ,  G11C7/10

Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

Abstract translation: 通过存储器接口连接到存储器控制器的模块的存储器空间可以用作命令缓冲器。 模块通过命令缓冲区接收的命令由模块执行。 存储器控制器可以无序地写入命令缓冲器。 存储器控制器可能会延迟或消除对命令缓冲区的写入。 与命令关联的标签用于指定执行顺序命令。 模块的存储空间中的状态缓冲区用于通信是否接收或执行了命令。 通过状态缓冲器接收的信息可以用作确定将命令重新发送到命令缓冲区的基础。

公开(公告)号：US09043513B2

公开(公告)日：2015-05-26

申请号：US14574156

申请日：2014-12-17

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Pradeep Batra ,  Steven Woo ,  Lawrence Lai ,  Chi-Ming Yeung

IPC: G06F9/26 ,  G06F12/02 ,  G06F12/10 ,  G06F13/42 ,  G06F12/00

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/10 ,  G06F13/385 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/251 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C14/0018 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract translation: 存储器系统包括将命令和地址传送到主存储器模块的CPU。 该模块包括缓冲电路，用于中继CPU和主存储器之间的命令和数据。 存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持外围功能，例如图形处理，以改善整体系统性能。 缓冲电路有助于CPU和外围处理器之间的指令和数据通信，以最小化或消除修改CPU的需要，从而减少采用具有集成处理能力的主存储器模块的实际障碍。

公开(公告)号：US20140237261A1

公开(公告)日：2014-08-21

申请号：US14133383

申请日：2013-12-18

Applicant: RAMBUS INC.

Inventor： Trung Am Diep ,  Pradeep Batra ,  Brian S. Leibowitz ,  Frederick A. Ware

IPC: G06F12/14

CPC classification number: G06F21/79 ,  G06F12/1009 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/30

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

Abstract translation: 存储器控制器至少部分地基于与页面帧相关联的帧密钥来加密页面帧的内容。 所述存储器控制器至少部分地基于与第一进程相关联的第一进程密钥来生成所述帧密钥的第一加密版本，其中所述帧密钥的所述第一加密版本被存储在与所述第一进程相关联的第一存储器表中。 所述存储器控制器至少部分地基于与第二进程相关联的第二进程密钥来生成所述帧密钥的第二加密版本，其中所述帧密钥的所述第二加密版本被存储在与所述第二进程相关联的第二存储器表中， 第一进程和第二进程分别使用帧密钥的第一加密版本和帧密钥的第二加密版本共享对页面帧的访问。

公开(公告)号：US20140173238A1

公开(公告)日：2014-06-19

申请号：US14098628

申请日：2013-12-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brian S. Leibowitz ,  Pradeep Batra ,  Trung Am Diep

IPC: G06F12/14

CPC classification number: G06F21/85 ,  G06F21/78 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/065 ,  H04L9/12 ,  H04L2209/12 ,  H04L2209/56

Abstract: Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.

Abstract translation: 描述了用于保护在存储器总线上共享并存储在存储器中的数据和指令的系统和方法。 用于写入和读取通道的独立且单独定时的流密码允许写入和读取事务之间的时序变化。 数据和指令可以在通道加密之前单独加密，以进一步保护信息。 垫片发生器和相关的加密电路被共享用于读取和写入数据，并且保护地址。 加密电路可以支持可变数据宽度，并且在一些实施例中，存储器设备包括可以使用重用存储器电路来实现共享密钥算法的安全电路。