公开(公告)号：US20230082649A1

公开(公告)日：2023-03-16

申请号：US17931125

申请日：2022-09-11

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US11469927B2

公开(公告)日：2022-10-11

申请号：US17110530

申请日：2020-12-03

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US20220172760A1

公开(公告)日：2022-06-02

申请号：US17531151

申请日：2021-11-19

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C5/06 ,  G11C5/02 ,  G11C8/18 ,  H01L25/065 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US20220070032A1

公开(公告)日：2022-03-03

申请号：US17400945

申请日：2021-08-12

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H04L25/03 ,  H01J37/00 ,  H01L21/311 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768 ,  H01L29/66

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US20210152402A1

公开(公告)日：2021-05-20

申请号：US17110530

申请日：2020-12-03

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US10855496B2

公开(公告)日：2020-12-01

申请号：US16057604

申请日：2018-08-07

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

IPC: H03H7/30 ,  H04B1/10 ,  H04L25/03 ,  G06F13/38

Abstract: An integrated circuit (IC) memory device includes receiver circuitry to receive write data from a memory controller. The receiver circuitry includes equalization circuitry having at least one tap to equalize the write data. The equalization circuitry includes a tap weight adapter circuit to adaptively generate a tap weight for the tap from an edge analysis of previously received write data.

公开(公告)号：US20200373169A1

公开(公告)日：2020-11-26

申请号：US16885948

申请日：2020-05-28

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/683 ,  H01L29/66 ,  H01L21/67 ,  H01J37/00

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US20200228376A1

公开(公告)日：2020-07-16

申请号：US16750924

申请日：2020-01-23

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US10700671B2

公开(公告)日：2020-06-30

申请号：US15824892

申请日：2017-11-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian S. Leibowitz ,  Jared Zerbe

IPC: H03K5/13 ,  G06F13/16 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22 ,  G06F13/42 ,  G06F13/00 ,  G11C7/04

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

公开(公告)号：US10686632B2

公开(公告)日：2020-06-16

申请号：US16182724

申请日：2018-11-07

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H04L25/03

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.