-
公开(公告)号：US20170097905A1
公开(公告)日：2017-04-06
申请号：US15333001
申请日：2016-10-24
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Amir Amirkhany , Suresh Rajan , Mohammad Hekmat , Dinesh Patil
CPC classification number: G06F13/1673 , G06F13/4068 , G11C5/02 , G11C7/10 , G11C7/1012 , G11C7/1021 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/022 , G11C29/023 , G11C29/028
Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
-
公开(公告)号：US09501433B2
公开(公告)日：2016-11-22
申请号：US14683080
申请日：2015-04-09
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Amir Amirkhany , Suresh Rajan , Mohammad Hekmat , Dinesh Patil
IPC: G06F13/00 , G06F13/16 , G11C7/10 , G11C8/18 , G11C11/419 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C5/02 , G11C29/02
CPC classification number: G06F13/1673 , G06F13/4068 , G11C5/02 , G11C7/10 , G11C7/1012 , G11C7/1021 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/022 , G11C29/023 , G11C29/028
Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
-
公开(公告)号：US09183920B2
公开(公告)日：2015-11-10
申请号：US14578078
申请日：2014-12-19
Applicant: RAMBUS INC.
Inventor： Frederick A. Ware , Suresh Rajan , Scott C. Best
IPC: G06F3/00 , G11C11/4093 , G11C5/04 , G11C11/408 , G06F12/06 , G06F13/16 , G11C7/10
CPC classification number: G11C11/4082 , G06F12/06 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C11/4076 , G11C11/4093
Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.
Abstract translation: 本文描述的实施例描述了在不同操作模式下使用存储器模块的技术，例如在标准多点模式或动态点对点（DPP）模式（此处也称为增强模式）中， 。 内存模块也可以以不同的配置插入存储系统的插座。
-
公开(公告)号：US09009400B2
公开(公告)日：2015-04-14
申请号：US14023970
申请日：2013-09-11
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Amir Amirkhany , Suresh Rajan , Mohammad Hekmat , Dinesh Patil
IPC: G06F13/00 , G11C7/10 , G11C8/18 , G11C11/419 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C29/02
CPC classification number: G06F13/1673 , G06F13/4068 , G11C5/02 , G11C7/10 , G11C7/1012 , G11C7/1021 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/022 , G11C29/023 , G11C29/028
Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
Abstract translation: 半导体存储器系统包括第一半导体存储器管芯和第二半导体存储器管芯。 第一半导体存储器管芯包括主数据接口，用于在写操作期间接收输入数据流，并将输入数据流反序列化为第一多个数据流，并且还包括耦合到主数据接口的辅数据接口， 发送第一多个数据流。 第二半导体存储器管芯包括耦合到第一半导体存储器管芯的次级数据接口的次级数据接口，以接收第一多个数据流。
-
公开(公告)号：US20250103531A1
公开(公告)日：2025-03-27
申请号：US18919179
申请日：2024-10-17
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
-
Patent Agency Ranking
公开(公告)号：US20240220141A1
公开(公告)日：2024-07-04
申请号：US18419933
申请日：2024-01-23
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
CPC classification number: G06F3/0635 , G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F13/1678 , Y02D10/00
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
-
公开(公告)号：US11907555B2
公开(公告)日：2024-02-20
申请号：US17989838
申请日：2022-11-18
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
CPC classification number: G06F3/0635 , G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F13/1678 , Y02D10/00
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
-
公开(公告)号：US11755521B2
公开(公告)日：2023-09-12
申请号：US17809688
申请日：2022-06-29
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
CPC classification number: G06F13/4022 , G06F12/00 , G06F13/00 , G06F13/1673 , G06F13/1694
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
-
公开(公告)号：US20230120661A1
公开(公告)日：2023-04-20
申请号：US17965684
申请日：2022-10-13
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Amir Amirkhany , Suresh Rajan , Mohammad Hekmat , Dinesh Patil
IPC: G06F13/16 , G11C7/10 , G11C8/18 , G11C11/419 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C5/02 , G06F13/40
Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
-
公开(公告)号：US11520508B2
公开(公告)日：2022-12-06
申请号：US16880244
申请日：2020-05-21
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
-
-
-
-
-
-
-
-
-
Search Results
83
records
(took 0.022 seconds)
