公开(公告)号：US20220189998A1

公开(公告)日：2022-06-16

申请号：US17687141

申请日：2022-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Kazuhiro KOUDATE

IPC: H01L27/12 ,  H03K3/356 ,  H03K19/00 ,  H03K3/012 ,  H03K19/0185

Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.

公开(公告)号：US20170076781A1

公开(公告)日：2017-03-16

申请号：US15224524

申请日：2016-07-30

Applicant: Renesas Electronics Corporation

Inventor： Kazuya UEJIMA

IPC: G11C11/406 ,  G11C14/00 ,  G11C13/00

CPC classification number: G11C14/009 ,  G11C7/1006 ,  G11C7/20 ,  G11C7/24 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C14/0045

Abstract: It is required to store data to be stored for a holding period required for this data and then erase the data while suppressing power consumption. A memory device 10 to solve such a problem has the following configuration. The memory device 10 includes an ReRAM (resistance random access memory) 100 and a storage controller 101. The storage controller 101 performs control to store, in a storing condition according to a holding period required for data to be stored, the data in the ReRAM 100.

Abstract translation: 需要将数据存储在该数据所需的保持期间，然后在抑制功耗的同时擦除数据。 解决这种问题的存储装置10具有以下结构。 存储装置10包括ReRAM（电阻随机存取存储器）100和存储控制器101.存储控制器101进行控制，以根据存储数据所需的保持期限的存储条件存储ReRAM中的数据 100。

公开(公告)号：US20150236156A1

公开(公告)日：2015-08-20

申请号：US14700461

申请日：2015-04-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Hidetatsu NAKAMURA ,  Akihito SAKAKIDANI ,  Eiichirou WATANABE

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/45 ,  H01L29/417

CPC classification number: H01L29/7843 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66636

Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.

Abstract translation: 半导体器件包括MISFET。 半导体器件还包括氮化硅膜12和布置在氮化硅膜12上的氮化硅膜10.氮化硅膜12覆盖MISFET的源极/漏极8的上部的至少一部分，并且具有 膜厚度比栅电极4的高度薄。源极/漏极8在其与氮化硅膜10的边界上包括硅化镍9。氮化硅膜10是应力膜。 氮化硅膜12与源极/漏极8的表面之间以及氮化硅膜12和氮化硅膜10之间的紧密附着性比使用氮化硅膜10 使其牢固地粘附到源/漏8。