公开(公告)号：US11276784B2

公开(公告)日：2022-03-15

申请号：US17121143

申请日：2020-12-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Okamoto ,  Nobuo Machida ,  Kenichi Hisada

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417 ,  H01L29/16 ,  H01L29/47

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

公开(公告)号：US10256339B2

公开(公告)日：2019-04-09

申请号：US16137279

申请日：2018-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasunori Yamashita ,  Koichi Arai ,  Kenichi Hisada

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51

Abstract: In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of apart of the gate insulating film part formed on/over a side face of the trench.

公开(公告)号：US20190096998A1

公开(公告)日：2019-03-28

申请号：US16035089

申请日：2018-07-13

Applicant: Renesas Electronics Corporation

Inventor： Yuji FUJII ,  Kenichi Hisada ,  Yasunori Yanashita

IPC: H01L29/16 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a metal film (Ni film) over the bottom surface of a contact hole that exposes a portion including SiC at the bottom surface, and performing a heat treatment to form a silicide film at the bottom surface of the contact hole by a silicidation reaction of the metal film MT and the portion including SiC. Also, the heat treatment step is a step of irradiating a laser beam on the surface of a SiC substrate. As the heat treatment, annealing is performed using the laser beam that goes through SiC and is absorbed by metal (Ni and the like).

公开(公告)号：US09922829B2

公开(公告)日：2018-03-20

申请号：US15206107

申请日：2016-07-08

Applicant: Renesas Electronics Corporation

Inventor： Koichi Arai ,  Kenichi Hisada

IPC: H01L29/10 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45

CPC classification number: H01L21/047 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p−type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n−-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p−-type body layer, and the n−-type drift layer between the p−-type body layer and the n−-type drift layer. By those measures, it is possible to inhibit the operating characteristic from varying.

公开(公告)号：US09466734B2

公开(公告)日：2016-10-11

申请号：US14325614

申请日：2014-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi Arai ,  Yasuaki Kagotoshi ,  Kenichi Hisada

IPC: H01L29/66 ,  H01L29/732 ,  H01L29/808 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/8083 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068

Abstract: To provide a semiconductor device having a vertical JFET excellent in off-state performance without reducing a production yield. A gate region quadrangular in the cross-section along a channel width direction is formed below a source region by impurity ion implantation. By first etching, the source region over the upper surface of the gate region is removed to separate therebetween. Then, the upper surface of the gate region is processed by second etching having an etching rate lower at the side surface than at the center of the gate region. The resulting gate region has a lower surface parallel to the substrate surface and an upper surface below a boundary between the source region and the channel formation region and having, in the cross-section along the channel width direction, a downward slope from the side surface to the center. As a result, a channel length with reduced variations can be obtained.

Abstract translation: 提供具有非常优异的截止状态的垂直JFET的半导体器件，而不降低产量。 通过杂质离子注入在源极区的下方形成沿通道宽度方向的截面中四边形的栅极区域。 通过首先蚀刻，去除栅极区域的上表面上方的源极区域以在其间分离。 然后，栅极区域的上表面通过第二蚀刻进行处理，其蚀刻速率在侧表面比在栅极区域的中心处更低。 所得到的栅极区域具有平行于基板表面的下表面和源区域和沟道形成区域之间的边界下方的上表面，并且在沿着沟道宽度方向的横截面中，从侧表面 到中心 结果，可以获得具有减小的变化的通道长度。