公开(公告)号：US20160043006A1

公开(公告)日：2016-02-11

申请号：US14882999

申请日：2015-10-14

Applicant: Renesas Electronics Corporation

Inventor： Kishou KANEKO ,  Hiroshi SUNAMURA ,  Yoshihiro HAYASHI

IPC: H01L21/8238 ,  H01L23/532 ,  H01L29/786

CPC classification number: H01L21/823828 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/53223 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer. A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.

Abstract translation: 本发明使得可以增加形成在布线层中的有源元件中的栅极绝缘膜的选择性。 根据本发明的半导体器件具有使用在作为栅极线的布线层中的Al线上形成的抗反射膜的底栅型晶体管。

公开(公告)号：US20150214218A1

公开(公告)日：2015-07-30

申请号：US14679385

申请日：2015-04-06

Applicant: Renesas Electronics Corporation

Inventor： Kishou KANEKO ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L27/06

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012

Abstract: A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.

Abstract translation: 半导体器件包括逻辑电路和有源元件电路。 逻辑电路设置有形成在半导体衬底中的半导体元件。 有源元件电路设置有使用在半导体衬底上形成的扩散绝缘膜上形成的半导体层形成的晶体管。 有源元件电路由逻辑电路控制。

公开(公告)号：US20130134418A1

公开(公告)日：2013-05-30

申请号：US13745291

申请日：2013-01-18

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro Hayashi ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L29/41

CPC classification number: H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

Abstract: A semiconductor device, includes a semiconductor substrate, a first interconnect layer formed over the semiconductor substrate, a gate electrode formed in the first interconnect layer, a gate insulating film formed over the gate electrode, a second interconnect layer formed over the gate insulating film, an oxide semiconductor layer formed in the second interconnect layer, and a via formed in the second interconnect layer and connected to the oxide semiconductor layer. The gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view.

Abstract translation: 一种半导体器件，包括半导体衬底，形成在半导体衬底上的第一互连层，形成在第一互连层中的栅电极，形成在栅电极上的栅极绝缘膜，形成在栅极绝缘膜上的第二互连层， 形成在第二互连层中的氧化物半导体层和形成在第二互连层中并连接到氧化物半导体层的通孔。 栅电极，栅极绝缘膜和氧化物半导体层在平面图中重叠。

公开(公告)号：US20160240625A1

公开(公告)日：2016-08-18

申请号：US15139563

申请日：2016-04-27

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L29/423 ,  H01L23/522 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/42384 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract translation: 本发明可以降低半导体元件的导通电阻，而不会妨碍具有使用布线层中的导线的半导体元件作为栅电极的半导体器件中的扩散防止膜的功能，并具有栅极绝缘膜 在与扩散防止膜相同的层中。 第一导线和栅电极嵌入到包括第一布线层的绝缘层的表面层中。 在第一布线层和第二布线层之间形成扩散防止膜。 栅极绝缘膜通过以下方式形成：在与栅电极重叠的区域和区域周围形成在扩散防止膜的上表面上的凹部; 并使部件变薄。

公开(公告)号：US20150056762A1

公开(公告)日：2015-02-26

申请号：US14527019

申请日：2014-10-29

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/42384 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract translation: 本发明可以降低半导体元件的导通电阻，而不会妨碍具有使用布线层中的导线的半导体元件作为栅电极的半导体器件中的扩散防止膜的功能，并具有栅极绝缘膜 在与扩散防止膜相同的层中。 第一导线和栅电极嵌入到包括第一布线层的绝缘层的表面层中。 在第一布线层和第二布线层之间形成扩散防止膜。 栅极绝缘膜通过以下方式形成：在与栅电极重叠的区域和区域周围形成在扩散防止膜的上表面上的凹部; 并使部件变薄。

公开(公告)号：US20140295657A1

公开(公告)日：2014-10-02

申请号：US14300836

申请日：2014-06-10

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76879 ,  H01L23/522 ,  H01L23/53223 ,  H01L23/5329 ,  H01L28/60 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.

Abstract translation: 公开了一种半导体器件，其在多层互连层中设置有源元件并且在芯片面积上减小。 在第一互连层上提供第二互连层。 第一层间绝缘层设置在第一互连层中。 半导体层设置在第二互连层中并与第一层间绝缘层接触。 在半导体层上设置栅极绝缘膜。 在栅绝缘膜上设置栅电极。 至少两个第一通孔设置在第一互连层中并且通过其上端与半导体层接触。

公开(公告)号：US20130200472A1

公开(公告)日：2013-08-08

申请号：US13738217

申请日：2013-01-10

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L21/76895 ,  H01L21/76849 ,  H01L21/823885 ,  H01L23/49822 ,  H01L27/0688 ,  H01L27/10858 ,  H01L27/1104 ,  H01L27/11551 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

Abstract translation: 提高了布置在多层布线层中的半导体元件的性能。 半导体器件包括：布置在第一布线层中的第一布线; 布置在层叠在第一布线层上的第二布线层中的第二布线; 栅电极，其在第一布线层和第二布线层的层叠方向上配置在第一布线和第二布线之间，不与第一布线和第二布线相连; 设置在所述栅电极的侧表面上的栅极绝缘膜; 以及通过栅极绝缘膜设置在栅电极的侧表面上并与第一线和第二线耦合的半导体层。

公开(公告)号：US20130181221A1

公开(公告)日：2013-07-18

申请号：US13710209

申请日：2012-12-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kishou KANEKO ,  Hiroshi SUNAMURA ,  Yoshihiro HAYASHI

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/786 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/12 ,  H01L27/1259 ,  H01L28/20 ,  H01L29/66742 ,  H01L2924/0002 ,  H03K19/00 ,  H01L2924/00

Abstract: A circuit including an inverter is provided for a wiring layer.A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.

Abstract translation: 为布线层设置包括逆变器的电路。 半导体器件设置有形成在绝缘膜上并且包括至少一个反相器元件的布线层电路。 逆变器设置有第一晶体管元件和电阻元件，其经由连接节点连接到第一晶体管。 第一晶体管元件设置有嵌入在包括绝缘膜的层间绝缘膜中的栅极电极，形成在层间绝缘膜和栅电极之上的栅极绝缘膜，以及形成在第一半导体层上的第一半导体层 源电极和漏电极之间的栅极绝缘膜。 电阻元件设置有用作电阻的第二半导体层。 第一半导体层和第二半导体层形成在同一层中。