公开(公告)号：US20240145552A1

公开(公告)日：2024-05-02

申请号：US18407264

申请日：2024-01-08

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L21/28 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

CPC classification number: H01L29/40111 ,  G11C11/223 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/30 ,  H01L29/517

Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

公开(公告)号：US20230066650A1

公开(公告)日：2023-03-02

申请号：US17847991

申请日：2022-06-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/11597 ,  G11C11/22

Abstract: A performance of a memory cell including a ferroelectric film is improved. Reliability of the memory cell is ensured. A semiconductor device having a memory cell includes: a plurality of semiconductor layers configuring a channel region; a pair of semiconductor layers SI2 provided so as to sandwich the plurality of semiconductor layers SI1 in an X direction, connected to the plurality of semiconductor layers SI1, and configuring a source region and a drain region; a plurality of paraelectric films IL covering outer peripheries of the plurality of semiconductor layers SI1, respectively; a bottom electrode BE covering outer peripheries of the plurality of paraelectric films IL between the pair of semiconductor layers SI2; a ferroelectric film FE formed on the bottom electrode BE; and a top electrode TE formed on the ferroelectric film FE.

公开(公告)号：US20200258990A1

公开(公告)日：2020-08-13

申请号：US16858857

申请日：2020-04-27

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L27/11568 ,  H01L21/3105 ,  H01L49/02

Abstract: To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.

公开(公告)号：US20190341395A1

公开(公告)日：2019-11-07

申请号：US16515352

申请日：2019-07-18

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/11563 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L29/792 ,  H01L29/45

Abstract: A method for manufacturing a semiconductor device to provide a Metal Insulator Semiconductor Field Effect Transistor (MISFET) in a first region of a semiconductor substrate includes forming a first gate insulating film on the semiconductor substrate in the first region, forming a first gate electrode containing silicon on the first gate insulating film, forming first impurity regions inside the semiconductor substrate so as to sandwich the first gate electrode in the first region, the first impurity regions configuring a part of a first source region and a part of a first drain region, forming a first silicide layer on the first impurity region, forming a first insulating film on the semiconductor substrate so as to cover the first gate electrode and the first silicide layer, polishing the first insulating film so as to expose the first gate electrode, and forming a second silicide layer on the first gate electrode.

公开(公告)号：US20190207009A1

公开(公告)日：2019-07-04

申请号：US16193877

申请日：2018-11-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

Abstract: In a ferroelectric memory having a ferroelectric film between a gate electrode and a semiconductor substrate, dielectric breakdown of a gate insulating film is prevented and the polarization performance of the ferroelectric film is enhanced to improve the performance of a semiconductor device. In a memory cell including a field effect transistor including a control gate electrode formed over the semiconductor substrate, between the control gate electrode and a main surface of the semiconductor substrate, a paraelectric film and the ferroelectric film are formed by being stacked in this order over the main surface of the semiconductor substrate.

公开(公告)号：US20190081058A1

公开(公告)日：2019-03-14

申请号：US16107036

申请日：2018-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/11568 ,  H01L27/11521 ,  H01L27/12 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  G11C16/04

Abstract: A memory gate electrode and a control gate electrode are formed to cover a fin projecting from the upper surface of a semiconductor substrate. A part of the fin which is covered by the memory gate electrode and the control gate electrode is sandwiched by a silicide layer as a part of a source region and a drain region of a memory cell. This silicide layer is formed as a silicide layer.

公开(公告)号：US20180233592A1

公开(公告)日：2018-08-16

申请号：US15952956

申请日：2018-04-13

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L27/11568 ,  H01L27/11573

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L21/28568 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

Abstract: A semiconductor device having a memory cell includes: a first gate electrode formed on a semiconductor substrate via a first insulating film; a second gate electrode formed on the semiconductor substrate via the second insulating film having a charge storage portion inside so as to be adjacent to the first gate electrode; a third insulating film interposed between the first gate electrode and the second gate electrode; a first source/drain region formed on a main surface of the semiconductor substrate; a first silicide layer formed in contact with an upper surface of the first source/drain region; a second silicide layer formed in contact with an upper surface of the first gate electrode; and a third silicide layer formed in contact with an upper surface of the second gate electrode. The first to third silicide layers contain platinum.

公开(公告)号：US20170278856A1

公开(公告)日：2017-09-28

申请号：US15509148

申请日：2015-03-17

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/11563 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/51

CPC classification number: H01L27/11563 ,  H01L21/28052 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/792

Abstract: An MISFET has a gate electrode formed on a semiconductor substrate via a gate insulating film, and a source region and a drain region formed inside the semiconductor substrate so as to sandwich the gate electrode. And, a first silicide layer is formed on surfaces of the source region and the drain region, and a second silicide layer is formed on a surface of the gate electrode. Each of the first silicide layer and the second silicide layer is made of a first metal and silicon, and further contains a second metal different from the first metal. And, a concentration of the second metal inside the second silicide layer is lower than a concentration of the second metal inside the first silicide layer.

公开(公告)号：US20250046612A1

公开(公告)日：2025-02-06

申请号：US18776808

申请日：2024-07-18

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI ,  Shinji INOUE

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: The reliability of a semiconductor device is improved. In this disclosure, a gate insulating film is formed on a silicon carbide semiconductor substrate in a process using a material gas containing a halogen element and a metal element by an ALD method.

公开(公告)号：US20230187550A1

公开(公告)日：2023-06-15

申请号：US18163046

申请日：2023-02-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L29/78 ,  H01L21/28 ,  G11C11/22 ,  H01L23/522 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/40111 ,  G11C11/221 ,  G11C11/223 ,  H01L23/5226 ,  H01L29/42364 ,  H01L29/6684 ,  G11C11/2273 ,  G11C11/2275

Abstract: A Semiconductor device includes a semiconductor substrate, an insulating film, a first conductive film, a ferroelectric film, an insulating layer, a first plug and a second plug. The semiconductor substrate includes a source region and a drain region which are formed on a main surface thereof. The insulating film is formed on the semiconductor substrate such that the insulating film is located between the source region and the drain region in a plan view. The first conductive film is formed on the insulating film. The ferroelectric film is formed on the first conductive film. The insulating layer covers the first conductive film and the ferroelectric film. The first plug reaches the first conductive film. The second plug reaches the ferroelectric film. A material of the ferroelectric film includes hafnium and oxygen. In plan view, a size of the ferroelectric film is smaller than a size of the insulating film.