公开(公告)号：US20150056778A1

公开(公告)日：2015-02-26

申请号：US14516164

申请日：2014-10-16

Applicant: Renesas Electronics Corporation

Inventor： Kenzo MANABE ,  Naoya INOUE ,  Kenichiro HIJIOKA ,  Yoshihiro HAYASHI

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L27/1085 ,  H01L21/768 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Abstract translation: 一种半导体器件，包括：多层布线层，位于基板的上方，其中堆叠由布线和绝缘层构成的多个布线层; 存储电路，其形成在所述基板的存储电路区域中，并且具有嵌入在位于所述多层布线层中的凹部的电容元件; 形成在基板的逻辑电路区域中的逻辑电路; 层叠在由下部电极，电容绝缘膜和上部电极构成的电容元件上的上部耦合布线; 以及形成在构成逻辑电路的布线的上表面上的盖层。 上部连接线的上表面和盖膜的上表面设置在同一平面上。

公开(公告)号：US20130153888A1

公开(公告)日：2013-06-20

申请号：US13682297

申请日：2012-11-20

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76814 ,  H01L21/76879 ,  H01L23/522 ,  H01L23/53223 ,  H01L23/5329 ,  H01L28/60 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.

Abstract translation: 公开了一种半导体器件，其在多层互连层中设置有源元件并且在芯片面积上减小。 在第一互连层上提供第二互连层。 第一层间绝缘层设置在第一互连层中。 半导体层设置在第二互连层中并与第一层间绝缘层接触。 在半导体层上设置栅极绝缘膜。 在栅绝缘膜上设置栅电极。 至少两个第一通孔设置在第一互连层中并且通过其上端与半导体层接触。

公开(公告)号：US20130092993A1

公开(公告)日：2013-04-18

申请号：US13652944

申请日：2012-10-16

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro HIJIOKA ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10835 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/91 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.

Abstract translation: 半导体器件包括衬底，层间绝缘层，第一晶体管，多层互连层，电容器件，金属互连和第一触点。 层间绝缘膜设置在基板上。 将第一晶体管设置在衬底上并埋在层间绝缘层中。 第一晶体管至少具有栅电极和扩散电极。 多层互连层设置在层间绝缘膜的上方。 电容器件设置在多层互连层中。 金属互连与栅电极的上表面接触并埋在层间绝缘层中。 第一触点耦合到第一晶体管的扩散层并且被埋在层间绝缘层中。 金属互连包括与第一接触相同的材料。

公开(公告)号：US20180352434A1

公开(公告)日：2018-12-06

申请号：US15955831

申请日：2018-04-18

Applicant: Renesas Electronics Corporation

Inventor： Tomohiko OHTSU ,  Shinichi YAMADA ,  Yuichi MARUYAMA ,  Hideyuki WAKADA ,  Yoshihiro HAYASHI ,  Taku FUJIWARA

IPC: H04W12/06 ,  H04L29/06

Abstract: Provided is a technology for a technology for easily inhibiting a wireless signal from being spoofed. A wireless communication system includes a beacon device and an information processing terminal. The beacon device includes a first communication circuit for transmitting a beacon signal to the information processing terminal in accordance with a predetermined transmission interval pattern. The information processing terminal includes a second communication circuit, a first storage device, and a control device. The second communication circuit receives the beacon signal from the beacon device. The first storage device stores the predetermined transmission interval pattern. The control device authenticates the beacon device by comparing a reception interval pattern of the beacon signal received by the second communication circuit with the predetermined transmission interval pattern stored in the first storage device.

公开(公告)号：US20160240564A1

公开(公告)日：2016-08-18

申请号：US15139782

申请日：2016-04-27

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Kishou KANEKO ,  Naoya FURUTAKE ,  Shinobu SAITOU ,  Yoshihiro HAYASHI

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/477 ,  H01L29/24 ,  H01L27/092

CPC classification number: H01L27/1225 ,  H01L21/477 ,  H01L21/8254 ,  H01L27/0922 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/242 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/812

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.

公开(公告)号：US20160043006A1

公开(公告)日：2016-02-11

申请号：US14882999

申请日：2015-10-14

Applicant: Renesas Electronics Corporation

Inventor： Kishou KANEKO ,  Hiroshi SUNAMURA ,  Yoshihiro HAYASHI

IPC: H01L21/8238 ,  H01L23/532 ,  H01L29/786

CPC classification number: H01L21/823828 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/53223 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer. A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.

Abstract translation: 本发明使得可以增加形成在布线层中的有源元件中的栅极绝缘膜的选择性。 根据本发明的半导体器件具有使用在作为栅极线的布线层中的Al线上形成的抗反射膜的底栅型晶体管。

公开(公告)号：US20150371945A1

公开(公告)日：2015-12-24

申请号：US14843549

申请日：2015-09-02

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro HIJIOKA ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L23/528 ,  H01L29/94 ,  H01L23/532 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10835 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/91 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.

Abstract translation: 半导体器件包括衬底，层间绝缘层，第一晶体管，多层互连层，电容器件，金属互连和第一触点。 层间绝缘膜设置在基板上。 将第一晶体管设置在衬底上并埋在层间绝缘层中。 第一晶体管至少具有栅电极和扩散电极。 多层互连层设置在层间绝缘膜的上方。 电容器件设置在多层互连层中。 金属互连与栅电极的上表面接触并埋在层间绝缘层中。 第一触点耦合到第一晶体管的扩散层并且被埋在层间绝缘层中。 金属互连包括与第一接触相同的材料。

公开(公告)号：US20150236091A1

公开(公告)日：2015-08-20

申请号：US14701828

申请日：2015-05-01

Applicant: Renesas Electronics Corporation

Inventor： Hironori YAMAMOTO ,  Fuminori ITO ,  Yoshihiro HAYASHI

IPC: H01L29/06 ,  H01B3/46 ,  H01L23/535

CPC classification number: H01L29/0657 ,  H01B3/46 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/228 ,  H01L29/02 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.

Abstract translation: 多孔绝缘膜的沉积速率提高，多孔绝缘膜的膜强度提高。 两种以上的具有环状SiO结构作为主要骨架并且具有相互不同结构的有机硅氧烷原料被蒸发并用载气输送到反应器（室），并且包含氧原子的氧化剂气体是 加入。 因此，在反应器（室）中通过等离子体CVD（化学气相沉积）法或等离子体聚合法形成多孔绝缘膜。 在该步骤中，添加的氧化剂气体的流量与载气的流量的比率大于0和0.08以下。

公开(公告)号：US20150214218A1

公开(公告)日：2015-07-30

申请号：US14679385

申请日：2015-04-06

Applicant: Renesas Electronics Corporation

Inventor： Kishou KANEKO ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L27/06

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012

Abstract: A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.

Abstract translation: 半导体器件包括逻辑电路和有源元件电路。 逻辑电路设置有形成在半导体衬底中的半导体元件。 有源元件电路设置有使用在半导体衬底上形成的扩散绝缘膜上形成的半导体层形成的晶体管。 有源元件电路由逻辑电路控制。

公开(公告)号：US20140080228A1

公开(公告)日：2014-03-20

申请号：US14022565

申请日：2013-09-10

Applicant: Renesas Electronics Corporation

Inventor： Makoto UEKI ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

Abstract translation: 一种半导体器件，其中MRAM形成在包含在多层布线层中的布线层A中，所述MRAM具有与形成在布线层中并彼此绝缘的第一布线接触的至少两个第一磁化闭塞层，自由磁化 层在平面图中与两个第一磁化钉扎层重叠，并与第一磁化钉扎层，位于自由磁化层上方的非磁性层和位于非磁性层上的第二磁化钉扎层连接。