公开(公告)号：US20250015146A1

公开(公告)日：2025-01-09

申请号：US18763910

申请日：2024-07-03

Applicant: Renesas Electronics Corporation

Inventor： Yotaro GOTO

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A dielectric film, which contacts a field plate electrode, is formed between the field plate electrode and a gate electrode, and a recess is formed at an upper surface of the dielectric film and between a drain region and the gate electrode.

公开(公告)号：US20230335635A1

公开(公告)日：2023-10-19

申请号：US17722788

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Atsushi SAKAI ,  Yotaro GOTO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402

Abstract: A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

公开(公告)号：US20210376097A1

公开(公告)日：2021-12-02

申请号：US17316017

申请日：2021-05-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yotaro GOTO ,  Katsumi EIKYU ,  Yoshihiro NOMURA

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28

Abstract: A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has second and third insulating films adjacent to each other in a plan view and, in a gate length direction of the gate electrode, the second insulating film is located on an n-type source region side, and the third insulating film is located on an n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a laminated film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each bandgap of the three insulating films is larger than that of the second insulating film.

公开(公告)号：US20180358393A1

公开(公告)日：2018-12-13

申请号：US15937162

申请日：2018-03-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidenori SATO ,  Tatsuya KUNIKIYO ,  Yotaro GOTO

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/341

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H04N5/341 ,  H04N5/378

Abstract: In a solid-state imaging element having two or more photodiodes stacked in a vertical direction in each of pixels, electrons are prevented from moving between the respective photodiodes of the pixels adjacent to each other. The solid-state imaging element is formed by joining together a back surface of a first semiconductor wafer including one of the photodiodes and a wiring layer and a back surface of a second semiconductor wafer including another of the photodiodes and a wiring layer. By forming a first isolation region extending through a first semiconductor substrate forming the first semiconductor wafer and a second isolation region extending through a second semiconductor substrate forming the second semiconductor wafer, the photodiodes of one of the pixels are isolated from another of the pixels.

公开(公告)号：US20180350861A1

公开(公告)日：2018-12-06

申请号：US15934484

申请日：2018-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya KUNIKIYO ,  Hidenori SATO ,  Yotaro GOTO ,  Fumitoshi TAKAHASHI

IPC: H01L27/146

CPC classification number: H01L27/14609 ,  H01L27/14623 ,  H01L27/14632

Abstract: A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to charge and a transistor which converts the charge obtained in the photoelectric conversion element to voltage. A photodiode and a charge read transistor which are included in a pixel in the CMOS solid-state imaging element are provided in a semiconductor substrate, while an amplification transistor included in the foregoing pixel is provided in a semiconductor layer provided over the semiconductor substrate via a buried insulating layer. In the semiconductor substrate located in a buried insulating layer region, a p+-type back-gate semiconductor region for controlling a threshold voltage of the amplification transistor is provided.

公开(公告)号：US20170309668A1

公开(公告)日：2017-10-26

申请号：US15648362

申请日：2017-07-12

Applicant: Renesas Electronics Corporation

Inventor： Yotaro GOTO

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14683

Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.