公开(公告)号：US20180366508A1

公开(公告)日：2018-12-20

申请号：US15983029

申请日：2018-05-17

Applicant: Renesas Electronics Corporation

Inventor： Yotaro GOTO ,  Tatsuya KUNIKIYO ,  Hidenori SATO

IPC: H01L27/146 ,  H01L23/00

Abstract: In a solid state image sensor having two semiconductor substrates or more laminated longitudinally, electrical connection between the semiconductor substrates is made by a fine plug. An insulating film covering a first rear surface of a semiconductor substrate having a light receiving element, and an interlayer insulating film covering a second main surface of a semiconductor substrate mounting a semiconductor element are joined to each other. In its joint surface, a plug penetrating the insulating film and a lug embedded in a connection hole in an upper surface of the interlayer insulating film are joined, and the light receiving element and the semiconductor element are electrically connected through the plugs.

公开(公告)号：US20170213862A1

公开(公告)日：2017-07-27

申请号：US15365344

申请日：2016-11-30

Applicant: Renesas Electronics Corporation

Inventor： Takeshi KAMINO ,  Yotaro GOTO

IPC: H01L27/146

CPC classification number: H01L27/14605 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14643

Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes a pixel including a first active region where a photodiode and a transfer transistor are formed and a second active region for supplying a grounding potential. Over a p-type semiconductor region in the second active region, a plug for supplying the grounding potential is disposed. In an n-type semiconductor region for a drain region of the transfer transistor formed in the first active region, a gettering element is introduced. However, in the p-type semiconductor region in the second active region, the gettering element is not introduced.

公开(公告)号：US20240055301A1

公开(公告)日：2024-02-15

申请号：US18336203

申请日：2023-06-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yudai HIGA ,  Atsushi SAKAI ,  Yotaro GOTO

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L27/088 ,  H01L21/823475

Abstract: A semiconductor device includes a cell region in which MISFETs are formed, and a peripheral region surrounding the cell region in plan view. In the cell region and the peripheral region, an n-type impurity region is formed in a semiconductor substrate. In the semiconductor substrate, an element isolation portion, a p-type impurity region, and an n-type impurity region are formed in the peripheral region so as to surround the cell region in plan view. A p-type impurity region and an n-type impurity region are formed in the semiconductor substrate in the cell region so as to contact the impurity region. The element isolation portion is located in the impurity region and is spaced apart from a junction interface between the impurity region and the impurity region.

公开(公告)号：US20230387294A1

公开(公告)日：2023-11-30

申请号：US18191486

申请日：2023-03-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yotaro GOTO

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/66689

Abstract: In a semiconductor substrate, an n-type source region, an n-type drain region, a first p-type semiconductor region, and a second p-type semiconductor region surrounding the n-type source region and the first p-type semiconductor region are formed. A gate electrode is formed on the semiconductor substrate between the n-type source region and the n-type drain region via a dielectric film GF. In the semiconductor substrate, a recessed portion is formed so as to penetrate through the n-type source region, and the first p-type semiconductor region is formed under the recessed portion.

公开(公告)号：US20170084658A1

公开(公告)日：2017-03-23

申请号：US15364456

申请日：2016-11-30

Applicant: Renesas Electronics Corporation

Inventor： Takeshi KAMINO ,  Yotaro GOTO

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/31116 ,  H01L27/14605 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/1462 ,  H01L27/14689 ,  H01L29/66568 ,  H01L29/6659

Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.

公开(公告)号：US20160233262A1

公开(公告)日：2016-08-11

申请号：US15017573

申请日：2016-02-05

Applicant: Renesas Electronics Corporation

Inventor： Yotaro GOTO

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14683

Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.

Abstract translation: 绝缘衬垫层具有位于像素区域的四个角中至少一个的垂直角的区域中的像素区域外部并具有从其中去除绝缘衬垫层的外部像素去除区域。

公开(公告)号：US20160064323A1

公开(公告)日：2016-03-03

申请号：US14835284

申请日：2015-08-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki SEKIKAWA ,  Hidenori SATO ,  Yotaro GOTO ,  Takuya MARUYAMA ,  Masaaki SHINOHARA

IPC: H01L23/528 ,  H01L27/146 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/31051 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L22/30 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/14603 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.

Abstract translation: 连接部分将铜基第一布线层与布置在第一扩散阻挡膜的上侧上的铜基第二布线层连接。 第一扩散阻挡膜包括在二维视图中形成在作为二维视图的局部区域的半导体电路区域中形成的第一开口区域和形成为与二维视图中的第一开口区域不同的开口区域的第二开口区域。 开口区域形成在与形成为允许连接部分穿过第一扩散阻挡膜的开口区域不同的区域中。 标记布线层设置在与第二布线层相同的层的正上方的第二开口区域的正上方。 第二扩散阻挡膜布置成与标记布线层的上表面接触。

公开(公告)号：US20180358394A1

公开(公告)日：2018-12-13

申请号：US15924171

申请日：2018-03-16

Applicant: Renesas Electronics Corporation

Inventor： Takeshi KAMINO ,  Fumitoshi TAKAHASHI ,  Yotaro GOTO

IPC: H01L27/146 ,  H01L29/40

CPC classification number: H01L27/14612 ,  H01L27/14689 ,  H01L29/401

Abstract: In order to improve the performance of a solid-state imaging device, the solid-state imaging device has a pixel including a photoelectric conversion unit and a transfer transistor, and fluorine is introduced to a gate electrode and a drain region (extension region and n+-type semiconductor region) of the transfer transistor included in the pixel.

公开(公告)号：US20180315789A1

公开(公告)日：2018-11-01

申请号：US15898197

申请日：2018-02-15

Applicant: Renesas Electronics Corporation

Inventor： Fumitoshi TAKAHASHI ,  Tatsuya KUNIKIYO ,  Hidenori SATO ,  Yotaro GOTO

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/1469

Abstract: A semiconductor device which improves the dark current characteristics and transfer efficiency of a back-surface irradiation CMOS image sensor without an increase in the area of a semiconductor chip. In the CMOS image sensor, a pixel includes a transfer transistor and a photodiode with a pn junction. In plan view, a reflecting layer is formed over an n-type region which configures the photodiode, through an isolation insulating film. The reflecting layer extends over the gate electrode of the transfer transistor through a cap insulating film. A first layer signal wiring is electrically coupled to both the gate electrode and the reflecting layer through a contact hole made in an interlayer insulating film over the gate electrode, so the same potential is applied to the gate electrode and the reflecting layer.

公开(公告)号：US20170062497A1

公开(公告)日：2017-03-02

申请号：US15189303

申请日：2016-06-22

Applicant: Renesas Electronics Corporation

Inventor： Yotaro GOTO

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14623 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689

Abstract: An imaging device and a manufacturing method of the imaging device are provided, which can lower the level of a dark current in an optical black pixel without forming a new layer such as a hydrogen diffusion preventing film.Both of an insulating layer over a photodiode arranged over an effective pixel region and an insulating layer over a photodiode arranged over an OB pixel region include silicon nitride, are formed of the same layer, and are coupled with each other.

Abstract translation: 布置在有效像素区域上的光电二极管上的绝缘层和布置在OB像素区域上的光电二极管上的绝缘层包括氮化硅，由相同的层形成并且彼此耦合。