公开(公告)号：US20240421234A1

公开(公告)日：2024-12-19

申请号：US18646495

申请日：2024-04-25

Applicant: Renesas Electronics Corporation

Inventor： Fumitoshi TAKAHASHI

IPC: H01L29/866 ,  G05F1/46 ,  G05F3/18 ,  H01L27/06 ,  H01L29/66

Abstract: In a semiconductor substrate, an n-type cathode region, an n-type well region, and a p-type anode region are formed. An impurity concentration of the cathode region is higher than an impurity concentration of the well region. In plan view, the anode region includes the cathode region, and the well region includes the anode region and the cathode region. A depth of the well region from an upper surface of the semiconductor substrate is greater than a depth of the anode region from the upper surface of the semiconductor substrate. A depth of the cathode region from the upper surface of the semiconductor substrate is greater than the respective depths of the anode region and the well region.

公开(公告)号：US20180350861A1

公开(公告)日：2018-12-06

申请号：US15934484

申请日：2018-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya KUNIKIYO ,  Hidenori SATO ,  Yotaro GOTO ,  Fumitoshi TAKAHASHI

IPC: H01L27/146

CPC classification number: H01L27/14609 ,  H01L27/14623 ,  H01L27/14632

Abstract: A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to charge and a transistor which converts the charge obtained in the photoelectric conversion element to voltage. A photodiode and a charge read transistor which are included in a pixel in the CMOS solid-state imaging element are provided in a semiconductor substrate, while an amplification transistor included in the foregoing pixel is provided in a semiconductor layer provided over the semiconductor substrate via a buried insulating layer. In the semiconductor substrate located in a buried insulating layer region, a p+-type back-gate semiconductor region for controlling a threshold voltage of the amplification transistor is provided.

公开(公告)号：US20170287965A1

公开(公告)日：2017-10-05

申请号：US15462963

申请日：2017-03-20

Applicant: Renesas Electronics Corporation

Inventor： Koji IIZUKA ,  Fumitoshi TAKAHASHI

IPC: H01L27/146 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L27/14636 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/48 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14683 ,  H01L2224/04042 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/049

Abstract: The semiconductor device includes a semiconductor substrate having a main surface and a back surface, an device isolation film, formed over the main surface of the semiconductor substrate and having a first surface making contact with the main surface and a second surface opposed to the first surface, a plate electrode disposed over the device isolation film in contact with the second surface of the device isolation film, and a pad electrode disposed adjacent to the first surface of the device isolation film and making contact with the plate electrode.The semiconductor substrate has a first opening that passes therethrough from the back surface to the main surface and exposes the device isolation film. The device isolation film has a second opening located in the first opening and exposes a part of the plate electrode. The pad electrode is formed in the second opening and extends over the first surface of the device isolation film.

公开(公告)号：US20180358394A1

公开(公告)日：2018-12-13

申请号：US15924171

申请日：2018-03-16

Applicant: Renesas Electronics Corporation

Inventor： Takeshi KAMINO ,  Fumitoshi TAKAHASHI ,  Yotaro GOTO

IPC: H01L27/146 ,  H01L29/40

CPC classification number: H01L27/14612 ,  H01L27/14689 ,  H01L29/401

Abstract: In order to improve the performance of a solid-state imaging device, the solid-state imaging device has a pixel including a photoelectric conversion unit and a transfer transistor, and fluorine is introduced to a gate electrode and a drain region (extension region and n+-type semiconductor region) of the transfer transistor included in the pixel.

公开(公告)号：US20180315789A1

公开(公告)日：2018-11-01

申请号：US15898197

申请日：2018-02-15

Applicant: Renesas Electronics Corporation

Inventor： Fumitoshi TAKAHASHI ,  Tatsuya KUNIKIYO ,  Hidenori SATO ,  Yotaro GOTO

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/1469

Abstract: A semiconductor device which improves the dark current characteristics and transfer efficiency of a back-surface irradiation CMOS image sensor without an increase in the area of a semiconductor chip. In the CMOS image sensor, a pixel includes a transfer transistor and a photodiode with a pn junction. In plan view, a reflecting layer is formed over an n-type region which configures the photodiode, through an isolation insulating film. The reflecting layer extends over the gate electrode of the transfer transistor through a cap insulating film. A first layer signal wiring is electrically coupled to both the gate electrode and the reflecting layer through a contact hole made in an interlayer insulating film over the gate electrode, so the same potential is applied to the gate electrode and the reflecting layer.

公开(公告)号：US20170062505A1

公开(公告)日：2017-03-02

申请号：US15216756

申请日：2016-07-22

Applicant: Renesas Electronics Corporation

Inventor： Fumitoshi TAKAHASHI

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14689

Abstract: In an imaging device, a multilayered wiring structure is formed so as to cover a photodiode and so forth in a pixel region and a pixel transistor in a peripheral circuit region. A passivation film is formed so as to cover the multilayered wiring structure. The passivation film is interposed between a fourth interlayer insulation film and a color filter and extends from the pixel region to the peripheral circuit region in contact with the fourth interlayer insulation film. The passivation film in the peripheral circuit region is formed with a film thickness that is thicker than that of the passivation film in the pixel region.

Abstract translation: 在成像装置中，形成多层布线结构，以覆盖像素区域中的光电二极管等和外围电路区域中的像素晶体管。 形成钝化膜以覆盖多层布线结构。 钝化膜插入在第四层间绝缘膜和滤色器之间，并且从像素区域延伸到与第四层间绝缘膜接触的外围电路区域。 外围电路区域中的钝化膜形成为比像素区域中的钝化膜厚的膜厚度。