公开(公告)号：US20150243735A1

公开(公告)日：2015-08-27

申请号：US14711771

申请日：2015-05-14

Applicant: Renesas Electronics Corporation

Inventor： Kazuo TOMITA ,  Toshiyuki OASHI ,  Hidenori SATO

IPC: H01L29/06 ,  H01L29/45 ,  H01L23/528 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L29/0696 ,  H01L21/823871 ,  H01L23/52 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/1095 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A gate interconnection portion (GHB) includes a first gate interconnection portion (GHB1), a second gate interconnection portion (GHB2), and a third gate interconnection portion (GHB3). The first gate interconnection portion (GHB1) is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region (PER). The second gate interconnection portion (GHB2) is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion (GHB1) toward the power supply interconnection, and extends across a boundary between the element formation region (PER) and an element isolation insulating film (EB), which is in parallel to an X axis direction. The third gate interconnection portion (GHB3) further extends in parallel to the Y-axis direction from the second gate interconnection portion (GHB2) toward the power supply interconnection.

Abstract translation: 门互连部分（GHB）包括第一栅极互连部分（GHB1），第二栅极互连部分（GHB2）和第三栅极互连部分（GHB3）。 第一栅极互连部分（GHB1）平行于Y轴方向朝向电源互连形成，并延伸到元件形成区域（PER）内的规定位置。 第二栅极互连部（GHB2）与从第一栅极互连部（GHB1）朝向电源互连方向相对于Y轴方向倾斜地弯曲的方向平行地形成，并且跨越元件形成区域 （PER）和与X轴方向平行的元件隔离绝缘膜（EB）。 第三栅极互连部分（GHB3）还从第二栅极互连部分（GHB2）朝着电源互连方向平行于Y轴方向延伸。

公开(公告)号：US20180358393A1

公开(公告)日：2018-12-13

申请号：US15937162

申请日：2018-03-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidenori SATO ,  Tatsuya KUNIKIYO ,  Yotaro GOTO

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/341

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H04N5/341 ,  H04N5/378

Abstract: In a solid-state imaging element having two or more photodiodes stacked in a vertical direction in each of pixels, electrons are prevented from moving between the respective photodiodes of the pixels adjacent to each other. The solid-state imaging element is formed by joining together a back surface of a first semiconductor wafer including one of the photodiodes and a wiring layer and a back surface of a second semiconductor wafer including another of the photodiodes and a wiring layer. By forming a first isolation region extending through a first semiconductor substrate forming the first semiconductor wafer and a second isolation region extending through a second semiconductor substrate forming the second semiconductor wafer, the photodiodes of one of the pixels are isolated from another of the pixels.

公开(公告)号：US20180350861A1

公开(公告)日：2018-12-06

申请号：US15934484

申请日：2018-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya KUNIKIYO ,  Hidenori SATO ,  Yotaro GOTO ,  Fumitoshi TAKAHASHI

IPC: H01L27/146

CPC classification number: H01L27/14609 ,  H01L27/14623 ,  H01L27/14632

Abstract: A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to charge and a transistor which converts the charge obtained in the photoelectric conversion element to voltage. A photodiode and a charge read transistor which are included in a pixel in the CMOS solid-state imaging element are provided in a semiconductor substrate, while an amplification transistor included in the foregoing pixel is provided in a semiconductor layer provided over the semiconductor substrate via a buried insulating layer. In the semiconductor substrate located in a buried insulating layer region, a p+-type back-gate semiconductor region for controlling a threshold voltage of the amplification transistor is provided.

公开(公告)号：US20160064323A1

公开(公告)日：2016-03-03

申请号：US14835284

申请日：2015-08-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki SEKIKAWA ,  Hidenori SATO ,  Yotaro GOTO ,  Takuya MARUYAMA ,  Masaaki SHINOHARA

IPC: H01L23/528 ,  H01L27/146 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/31051 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L22/30 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/14603 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.

Abstract translation: 连接部分将铜基第一布线层与布置在第一扩散阻挡膜的上侧上的铜基第二布线层连接。 第一扩散阻挡膜包括在二维视图中形成在作为二维视图的局部区域的半导体电路区域中形成的第一开口区域和形成为与二维视图中的第一开口区域不同的开口区域的第二开口区域。 开口区域形成在与形成为允许连接部分穿过第一扩散阻挡膜的开口区域不同的区域中。 标记布线层设置在与第二布线层相同的层的正上方的第二开口区域的正上方。 第二扩散阻挡膜布置成与标记布线层的上表面接触。

公开(公告)号：US20180366508A1

公开(公告)日：2018-12-20

申请号：US15983029

申请日：2018-05-17

Applicant: Renesas Electronics Corporation

Inventor： Yotaro GOTO ,  Tatsuya KUNIKIYO ,  Hidenori SATO

IPC: H01L27/146 ,  H01L23/00

Abstract: In a solid state image sensor having two semiconductor substrates or more laminated longitudinally, electrical connection between the semiconductor substrates is made by a fine plug. An insulating film covering a first rear surface of a semiconductor substrate having a light receiving element, and an interlayer insulating film covering a second main surface of a semiconductor substrate mounting a semiconductor element are joined to each other. In its joint surface, a plug penetrating the insulating film and a lug embedded in a connection hole in an upper surface of the interlayer insulating film are joined, and the light receiving element and the semiconductor element are electrically connected through the plugs.

公开(公告)号：US20190273108A1

公开(公告)日：2019-09-05

申请号：US16278941

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidenori SATO ,  Koji IIZUKA ,  Takeshi KAMINO

IPC: H01L27/146 ,  H01L23/00

Abstract: A hybrid-bonding-type solid-state imaging device is provided that prevents moisture from entering through the bonded interface and other areas. The solid-state imaging device includes a first interconnect structure over a sensor substrate and a second interconnect structure over a logic substrate, and the first and second interconnect structures are bonded together. At the bonded surface between the first and second interconnect structures, bonding pads formed in the first interconnect structure are bonded to bonding pads formed in the second interconnect structure. Eighth layer portions of a first seal ring formed in the first interconnect structure are bonded to eighth layer portions of a second seal ring formed in the second interconnect structure.

公开(公告)号：US20180315789A1

公开(公告)日：2018-11-01

申请号：US15898197

申请日：2018-02-15

Applicant: Renesas Electronics Corporation

Inventor： Fumitoshi TAKAHASHI ,  Tatsuya KUNIKIYO ,  Hidenori SATO ,  Yotaro GOTO

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/1469

Abstract: A semiconductor device which improves the dark current characteristics and transfer efficiency of a back-surface irradiation CMOS image sensor without an increase in the area of a semiconductor chip. In the CMOS image sensor, a pixel includes a transfer transistor and a photodiode with a pn junction. In plan view, a reflecting layer is formed over an n-type region which configures the photodiode, through an isolation insulating film. The reflecting layer extends over the gate electrode of the transfer transistor through a cap insulating film. A first layer signal wiring is electrically coupled to both the gate electrode and the reflecting layer through a contact hole made in an interlayer insulating film over the gate electrode, so the same potential is applied to the gate electrode and the reflecting layer.

公开(公告)号：US20170365631A1

公开(公告)日：2017-12-21

申请号：US15624357

申请日：2017-06-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji IIZUKA ,  Hidenori SATO

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/14689

Abstract: To provide a solid state image sensor having improved sensitivity and at the same time, causing less dark current, noise, and the like. In a solid state image sensor having a substrate comprised of an N type semiconductor substrate and a P type epitaxial layer thereon, formed are a trench penetrating the epitaxial layer in an isolation region between a pixel region having therein array of pixels and a peripheral circuit region around the pixel region; and a DTI structure comprised of an insulating film with which the trench is filled. Transfer of electrons in the substrate between the pixel region and the peripheral circuit region is thereby prevented.