Method And System For Improving Quality Of Communication Based On Label Distribution Protocol
    12.
    发明申请
    Method And System For Improving Quality Of Communication Based On Label Distribution Protocol 有权
    基于标签分发协议提高通信质量的方法与系统

    公开(公告)号:US20090028148A1

    公开(公告)日:2009-01-29

    申请号:US12212300

    申请日:2008-09-17

    申请人: Wei Cao Xiaohu Xu

    发明人: Wei Cao Xiaohu Xu

    IPC分类号: H04L12/56

    摘要: A method and system for improving a quality of communication based on a label distribution protocol is provided. The method includes the following: When a local label switching router (LSR) finds out a change of a route at an upstream node in a multicast label switching path (LSP), it calculates and sets up a new optimized multicast LSP according to the label distribution protocol (LDP), and delays to send a withdraw request to the upstream node in the former multicast LSP. An interruption of the data stream in the multicast LSP reconstruction procedures can be avoided or reduced, so that the loss of data packets caused by the multicast LSP adjustment is reduced, and the quality of communication of the multicast is improved.

    摘要翻译: 提供了一种基于标签分发协议提高通信质量的方法和系统。 该方法包括:当本地标签交换路由器(LSR)发现组播标签交换路径(LSP)上游节点的路由发生变化时,根据标签计算并建立新的优化组播LSP 分发协议(LDP),并将延迟发送到前一个组播LSP中的上游节点。 可以避免或减少组播LSP重建过程中的数据流的中断,从而降低由组播LSP调整引起的数据包丢失,提高组播通信质量。

    Bottom conductor for integrated MRAM
    13.
    发明申请
    Bottom conductor for integrated MRAM 有权
    集成MRAM的底部导体

    公开(公告)号:US20070281427A1

    公开(公告)日:2007-12-06

    申请号:US11891923

    申请日:2007-08-14

    IPC分类号: H01L21/336

    CPC分类号: H01L43/12 H01L27/228

    摘要: A method to fabricate an MTJ device and its connections to a CMOS integrated circuit is described. The device is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum.

    摘要翻译: 描述了制造MTJ器件及其与CMOS集成电路的连接的方法。 该设备由三层构建。 底层用作中心层的种子层,其为α钽,而第三最顶层选择为其平滑度,其与层间电介质材料的相容性以及其保护下面的钽的能力。

    Bottom conductor for integrated MRAM
    14.
    发明授权
    Bottom conductor for integrated MRAM 有权
    集成MRAM的底部导体

    公开(公告)号:US07265404B2

    公开(公告)日:2007-09-04

    申请号:US11215276

    申请日:2005-08-30

    IPC分类号: H01L29/76

    CPC分类号: H01L43/12 H01L27/228

    摘要: A structure that is well suited to connecting an MTJ device to a CMOS integrated circuit is described. It is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum. A method for its formation is also described.

    摘要翻译: 描述了非常适合于将MTJ设备连接到CMOS集成电路的结构。 它由三层构建。 底层用作中心层的种子层,其为α钽,而第三最顶层选择为其平滑度,其与层间电介质材料的相容性以及其保护下面的钽的能力。 还描述了其形成方法。

    Method of fabricating contact pad for magnetic random access memory
    15.
    发明授权
    Method of fabricating contact pad for magnetic random access memory 有权
    制造磁性随机存取存储器接触焊盘的方法

    公开(公告)号:US07122386B1

    公开(公告)日:2006-10-17

    申请号:US11231674

    申请日:2005-09-21

    IPC分类号: H01L21/00

    CPC分类号: H01L43/12 H01L27/222

    摘要: A method of forming a Cu—Cu junction between a word line pad (WLP) and bit line (BL) contact is described. An opening above a WL contact is formed in a first SiNx layer on a substrate that includes a WLP and word line. After a bottom electrode (BE) layer, MTJ stack, and hard mask are sequentially deposited, an etch forms an MTJ element above the word line. Another etch forms a BE and exposes the first SiNx layer above the WLP and bond pad (BP). An MTJ ILD layer is deposited and planarized followed by deposition of a second SiNx layer and BL ILD layer. Trenches are formed in the BL ILD layer and second SiNx layer above the WLP, hard mask and BP. After vias are formed in the MTJ ILD and first SiNx layers above the WLP and BP, Cu deposition follows to form dual damascene BL contacts.

    摘要翻译: 描述了在字线焊盘(WLP)和位线(BL)触点之间形成Cu-Cu结的方法。 在包括WLP和字线的衬底上的第一SiN x层中形成WL触点上方的开口。 在底电极(BE)层,MTJ叠层和硬掩模之后,顺序沉积,蚀刻在字线之上形成MTJ元件。 另一蚀刻形成BE,并使WLP和接合焊盘(BP)上方的第一SiN x层暴露。 沉积MTJ ILD层并平坦化,随后沉积第二SiN x层和BL ILD层。 沟槽形成在WLP,硬掩模和BP之上的BL ILD层和第二SiN x x层中。 在WLP和BP上方的MTJ ILD和第一SiN x x层中形成通孔之后,随后进行Cu沉积以形成双镶嵌BL触点。

    Multi-step barrier deposition method
    16.
    发明申请
    Multi-step barrier deposition method 失效
    多步势垒沉积法

    公开(公告)号:US20050255690A1

    公开(公告)日:2005-11-17

    申请号:US11184431

    申请日:2005-07-19

    摘要: A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rather than the target with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls and a second step sputter deposits a second barrier layer, for example of Ta/TaN, onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls.

    摘要翻译: 在穿过层间电介质层的通孔中形成阻挡层的方法,包括涂覆在通孔的底部和侧壁上的预先形成的第一屏障。 在单个等离子体溅射反应器中,第一步骤以高能离子将晶片而不是目标物喷射,以从通孔的底部除去阻挡层,而不是从侧壁排出,第二步骤溅射沉积第二阻挡层,例如 的Ta / TaN,通过底部和侧壁。 这两个步骤可以通过施加到靶,通过室压力或通过晶片偏置的功率来区分。 第二步骤可以包括从通孔底部同时移除第一阻挡层并将第二阻挡层溅射到通孔侧壁上。

    Method for growing thin films by catalytic enhancement
    17.
    发明授权
    Method for growing thin films by catalytic enhancement 失效
    通过催化增强生长薄膜的方法

    公开(公告)号:US06811814B2

    公开(公告)日:2004-11-02

    申请号:US10052049

    申请日:2002-01-16

    申请人: Ling Chen Wei Cao

    发明人: Ling Chen Wei Cao

    IPC分类号: C23C1618

    CPC分类号: C23C16/18 C23C16/45534

    摘要: A method of growing a thin film onto a substrate. A precursor of the film is fed into a reaction space in the form of a vapor phase pulse causing the precursor to adsorb onto the surface of the substrate to form a layer thereof. A catalyst is susequently fed into the reaction space in an amount to substantially convert the layer of the precursor to the desired thin film. The above steps may be repeated to achieve the desired film thickness.

    摘要翻译: 将薄膜生长到基底上的方法。 将膜的前体以气相脉冲的形式进料到反应空间中,使得前体吸附在基材的表面上以形成其层。 将催化剂以大量将前体的层基本上转化为所需的薄膜的量被充分地供给到反应空间中。 可以重复上述步骤以实现所需的膜厚度。

    Method, system, and device for establishing pseudo wire
    18.
    发明授权
    Method, system, and device for establishing pseudo wire 有权
    用于建立伪线的方法,系统和设备

    公开(公告)号:US09160655B2

    公开(公告)日:2015-10-13

    申请号:US13548880

    申请日:2012-07-13

    摘要: A method, a system, and a device for establishing a pseudo wire are disclosed. The method includes: receiving, by a switching provider edge at a bifurcation position, a label mapping message, obtaining information of the switching provider edge at the bifurcation position and information of at least two next hops or outgoing interfaces of the switching provider edge through parsing, comparing the information of the switching provider edge at the bifurcation position with information of a local device, and if the information of the switching provider edge at the bifurcation position matches with the information of the local device, establishing at least two pseudo wires from the switching provider edge according to the information of at least two next hops or outgoing interfaces.

    摘要翻译: 公开了一种用于建立伪线的方法,系统和装置。 该方法包括:通过分叉位置处的交换提供商边缘接收标签映射消息,通过解析获得交换提供商边缘的分叉位置处的交换提供商边缘的信息和交换提供商边缘的至少两个下一跳或出口接口的信息 将分叉位置处的交换提供商边缘的信息与本地设备的信息进行比较,并且如果分支位置处的切换提供商边缘的信息与本地设备的信息匹配,则从 根据至少两个下一跳或出站接口的信息切换提供商边缘。

    Magnetic tunnel junction for MRAM applications
    19.
    发明授权
    Magnetic tunnel junction for MRAM applications 有权
    用于MRAM应用的磁隧道结

    公开(公告)号:US08786036B2

    公开(公告)日:2014-07-22

    申请号:US12930877

    申请日:2011-01-19

    IPC分类号: H01L43/10 H01L27/22

    摘要: A MTJ in an MRAM array is disclosed with a composite free layer having a lower crystalline layer contacting a tunnel barrier and an upper amorphous NiFeX layer for improved bit switching performance. The crystalline layer is Fe, Ni, or FEB with a thickness of at least 6 Angstroms which affords a high magnetoresistive ratio. The X element in the NiFeX layer is Mg, Hf, Zr, Nb, or Ta with a content of 5 to 30 atomic % NiFeX thickness is preferably between 20 to 40 Angstroms to substantially reduce bit line switching current and number of shorted bits. In an alternative embodiments, the crystalline layer may be a Fe/NiFe bilayer. Optionally, the amorphous layer may have a NiFeM1/NiFeM2 configuration where M1 and M2 are Mg, Hf, Zr, Nb, or Ta, and M1 is unequal to M2. Annealing at 300° C. to 360° C. provides a high magnetoresistive ratio of about 150%.

    摘要翻译: 公开了具有接触隧道势垒的较低结晶层和上部非晶NiFeX层的复合自由层的MRAM阵列中的MTJ,用于改善位切换性能。 结晶层是厚度至少为6埃的Fe,Ni或FEB,其具有高的磁阻比。 NiFeX层中的X元素为含有5〜30原子%NiFeX厚度的Mg,Hf,Zr,Nb或Ta优选为20〜40埃,以显着降低位线切换电流和短路位数。 在替代实施例中,结晶层可以是Fe / NiFe双层。 可选地,非晶层可以具有其中M1和M2是Mg,Hf,Zr,Nb或Ta的NiFeM1 / NiFeM2构型,M1不等于M2。 在300℃至360℃退火,提供约150%的高磁阻比。