Led in substrate with back side monitoring
    11.
    发明授权
    Led in substrate with back side monitoring 失效
    带背面监测基板

    公开(公告)号:US06248600B1

    公开(公告)日:2001-06-19

    申请号:US09409976

    申请日:1999-09-30

    IPC分类号: H01L2100

    CPC分类号: H01L21/306

    摘要: Post-manufacturing analysis of a semiconductor device is enhanced via a method that uses a light emitting diode (LED) formed in a semiconductor die. According to an example embodiment of the present invention, a LED is formed within a semiconductor die having a circuit side opposite a back side. The LED is activated and generates radiation. Substrate is removed from the device, and the amount of radiation that passes through the substrate is detected. The amount of radiation that passes through the die is a function of the absorption characteristics of the die and the substrate thickness. By detecting the radiation and using the absorption characteristics of the die, the amount of substrate remaining in the back side of the die is determined and the substrate removal process is controlled therefrom.

    摘要翻译: 通过使用形成在半导体管芯中的发光二极管(LED)的方法来增强半导体器件的制造后分析。 根据本发明的示例性实施例,在具有与背面相对的电路侧的半导体管芯内形成LED。 LED被激活并产生辐射。 从器件中去除衬底,并检测穿过衬底的辐射量。 通过模具的辐射量是模具的吸收特性和基板厚度的函数。 通过检测辐射并使用模具的吸收特性,确定保留在模具背面的基板的量,并从中控制基板去除过程。

    Magnetic resonance imaging of semiconductor devices
    13.
    发明授权
    Magnetic resonance imaging of semiconductor devices 失效
    半导体器件的磁共振成像

    公开(公告)号:US06529029B1

    公开(公告)日:2003-03-04

    申请号:US09409973

    申请日:1999-09-30

    IPC分类号: G01R3128

    CPC分类号: G01R31/303

    摘要: A method for detecting substrate damage in a flip chip die, having a back side and a circuit side, that uses magnetic resonance imaging. The back side of the die is first globally thinned down and a region for examination is selected. A magnetic field is applied to the selected region and then the region is scanned with a magnetic resonance imaging arrangement. A plurality of perturbations are measured to generate an array of perturbation signals, which are then converted to a local susceptibility map of the selected region of the die. The susceptibility map of the selected region is then examined to determine if there is any substrate damage.

    摘要翻译: 一种用于检测使用磁共振成像的具有背面和电路侧的倒装芯片的基板损伤的方法。 首先将模具的背面全局变薄,并选择检查区域。 将磁场施加到所选择的区域,然后用磁共振成像装置扫描该区域。 测量多个扰动以产生扰动信号阵列,然后将它们转换成所选择的模具区域的局部磁敏度图。 然后检查所选区域的磁敏度图,以确定是否存在任何底物损伤。

    Forming elongated probe points useful in testing semiconductor devices
    14.
    发明授权
    Forming elongated probe points useful in testing semiconductor devices 失效
    形成可用于测试半导体器件的细长探针点

    公开(公告)号:US06372529B1

    公开(公告)日:2002-04-16

    申请号:US09408616

    申请日:1999-09-30

    IPC分类号: G01R3126

    摘要: Access to portions of semiconductor devices is enhanced via a method and system for probing between circuitry in the semiconductor device during post-manufacture analysis of the semiconductor device. According to an example embodiment of the present invention, an elongated conductive via probe is formed in a semiconductor device having circuitry in a circuit side opposite a back side. The probe is formed by first removing substrate from the semiconductor device and forming an exposed region over a target node between circuitry in the device. A narrow conductor is then formed for accessing the target node, with the conductor and extending between the circuitry and into the back side and forming the elongated conductive via probe. The probe is accessed and used for analyzing the device. In this manner, access to a difficult-to-reach target node, such as a node between closely-placed transistors, is facilitated.

    摘要翻译: 通过用于在半导体器件的后制造分析期间在半导体器件中的电路之间探测的方法和系统来增强对半导体器件的部分的访问。 根据本发明的示例性实施例,在具有在背侧相反的电路侧中的电路的半导体器件中形成细长的导电通孔探针。 通过首先从半导体器件去除衬底并在器件中的电路之间的目标节点上形成暴露区域来形成探针。 然后形成窄导体,用于与导体接合目标节点,并在电路之间延伸并进入后侧,并形成细长的导电通孔探针。 探头被访问并用于分析设备。 以这种方式,便于访问难以达到的目标节点,诸如紧密放置的晶体管之间的节点。

    Substrate removal as a function of SIMS analysis
    16.
    发明授权
    Substrate removal as a function of SIMS analysis 失效
    基板去除作为SIMS分析的功能

    公开(公告)号:US06281025B1

    公开(公告)日:2001-08-28

    申请号:US09409320

    申请日:1999-09-30

    IPC分类号: H01L2100

    摘要: Substrate removal for post-manufacturing analysis of a semiconductor device is enhanced via a method and system that utilizes ion beam etching, to etch the backside of a semiconductor chip, and utilizes SIMS as a detection technique to not only control removal of the substrate from the backside of the chip but also to determine the endpoint of the removal process. In an example embodiment there is described a method for removing substrate from the backside of a semiconductor chip as a function of detected concentration levels of a selected substrate material that is sputtered off of a region of the substrate.

    摘要翻译: 通过利用离子束蚀刻,蚀刻半导体芯片的背面的方法和系统来增强对半导体器件的后制造分析的衬底去除,并且利用SIMS作为检测技术,不仅可以控制从衬底的去除 芯片的背面还可以确定去除过程的终点。 在一个示例性实施例中,描述了从半导体芯片的背面去除衬底的方法,其作为从衬底区域溅射的所选择的衬底材料的检测浓度水平的函数。

    Circuit construction in back side of die and over a buried insulator
    17.
    发明授权
    Circuit construction in back side of die and over a buried insulator 失效
    模具背面的电路结构和埋地绝缘子上方

    公开(公告)号:US06518783B1

    公开(公告)日:2003-02-11

    申请号:US09864669

    申请日:2001-05-23

    IPC分类号: H01L2166

    CPC分类号: G01R31/2884

    摘要: According to an example embodiment of the present invention, a semiconductor die having a buried insulator layer between a circuit side and a back side is selectively thinned. During thinning, a selected portion of the bulk silicon layer on the back side is removed and a void created. A circuit is formed in the void and is coupled to the existing circuitry on the circuit side of the die. The new circuit is used to analyze the die during operation, testing, or other conditions. The newly formed circuit enhances the ability to analyze the semiconductor die by adding flexibility to the traditional analysis methods used for integrated circuit dice. The newly formed circuit enables many new ways of interactively using the existing circuitry some of which include replacement of defective circuitry, modification of existing circuit operations, and stimulation of existing circuitry for testing.

    摘要翻译: 根据本发明的示例性实施例,选择性地减薄在电路侧和背面之间具有掩埋绝缘体层的半导体管芯。 在减薄期间,去除背面上的体硅层的选定部分并产生空隙。 在空隙中形成电路并且耦合到管芯电路侧上的现有电路。 新电路用于在运行,测试或其他条件下对芯片进行分析。 新形成的电路通过增加集成电路芯片的传统分析方法的灵活性,增强了半导体芯片的分析能力。 新形成的电路使得能够交互地使用现有电路的许多新方式,其中一些电路包括有缺陷电路的更换,现有电路操作的修改和用于测试的现有电路的刺激。

    Method and apparatus for stress testing a semiconductor device using laser-induced circuit excitation
    19.
    发明授权
    Method and apparatus for stress testing a semiconductor device using laser-induced circuit excitation 失效
    使用激光感应电路激励对半导体器件进行应力测试的方法和装置

    公开(公告)号:US06417680B1

    公开(公告)日:2002-07-09

    申请号:US09408663

    申请日:1999-09-29

    IPC分类号: G01R3102

    CPC分类号: G01R31/311

    摘要: According to an example embodiment, a laser is directed at a target region of a powered semiconductor device via the back side of the device, and active circuitry is selectively excited. In response to the excited circuitry, target circuitry is monitored and a degree of integrity of the operation of the semiconductor device is determined, for example, by detecting the output s/phase characteristics or by monitoring passive emissions from the device. The invention is particularly advantageous in connection with post-manufacture failure analysis.

    摘要翻译: 根据示例性实施例,激光器经由设备的背面被引导到有源半导体器件的目标区域,并且有选择地激励有源电路。 响应于激励电路,监视目标电路,并且例如通过检测输出s /相位特性或通过监视来自装置的被动发射来确定半导体器件的操作的完整程度。 本发明在制造后故障分析方面是特别有利的。