公开(公告)号：US11036398B2

公开(公告)日：2021-06-15

申请号：US16535814

申请日：2019-08-08

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G06F11/00 ,  G06F12/14 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16 ,  G11C7/10 ,  G06F11/14

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US10705912B2

公开(公告)日：2020-07-07

申请号：US15990078

申请日：2018-05-25

Applicant: Rambus Inc.

Inventor： Michael Miller ,  Stephen Magee ,  John Eric Linstadt

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

公开(公告)号：US20200004686A1

公开(公告)日：2020-01-02

申请号：US16453284

申请日：2019-06-26

Applicant: Rambus Inc.

Inventor： Michael Miller ,  Dennis Doidge ,  Collins Williams

IPC: G06F12/0895 ,  G06F12/0804 ,  G06F12/0864 ,  G06F9/38 ,  G06F12/0815

Abstract: A device includes a cache memory and a memory controller coupled to the cache memory. The memory controller is configured to receive a first read request from a cache controller over an interconnect, the first read request comprising first tag data identifying a first cache line in the cache memory, and determine that the first read request comprises a tag read request. The memory controller is further configured to read second tag data corresponding to the tag read request from the cache memory, compare the second tag data read from the cache memory to the first tag data received from the cache controller with the first read request, and if the second tag data matches the first tag data, initiate an action with respect to the first cache line in the cache memory.

公开(公告)号：US09946470B2

公开(公告)日：2018-04-17

申请号：US15156691

申请日：2016-05-17

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/0613 ,  G06F3/0611 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F11/00 ,  G06F12/0802 ,  G06F13/1668 ,  G06F13/1673 ,  G06F2212/1024 ,  G06F2212/205 ,  G11C5/04 ,  G11C7/1051 ,  G11C11/005 ,  G11C14/0009

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US20230418758A1

公开(公告)日：2023-12-28

申请号：US18214450

申请日：2023-06-26

Applicant: Rambus Inc.

Inventor： Michael Miller ,  Dennis Doidge ,  Collins Williams

IPC: G06F12/0895 ,  G06F12/0804 ,  G06F12/0815 ,  G06F9/38 ,  G06F12/0864

CPC classification number: G06F12/0895 ,  G06F12/0804 ,  G06F12/0815 ,  G06F9/3816 ,  G06F12/0864

Abstract: A device includes a cache memory and a memory controller coupled to the cache memory. The memory controller is configured to receive a first read request from a cache controller over an interconnect, the first read request comprising first tag data identifying a first cache line in the cache memory, and determine that the first read request comprises a tag read request. The memory controller is further configured to read second tag data corresponding to the tag read request from the cache memory, compare the second tag data read from the cache memory to the first tag data received from the cache controller with the first read request, and if the second tag data matches the first tag data, initiate an action with respect to the first cache line in the cache memory.

公开(公告)号：US11726920B2

公开(公告)日：2023-08-15

申请号：US16453284

申请日：2019-06-26

Applicant: Rambus Inc.

Inventor： Michael Miller ,  Dennis Doidge ,  Collins Williams

IPC: G06F12/0895 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0864 ,  G06F9/38

CPC classification number: G06F12/0895 ,  G06F9/3816 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0864

Abstract: A device includes a cache memory and a memory controller coupled to the cache memory. The memory controller is configured to receive a first read request from a cache controller over an interconnect, the first read request comprising first tag data identifying a first cache line in the cache memory, and determine that the first read request comprises a tag read request. The memory controller is further configured to read second tag data corresponding to the tag read request from the cache memory, compare the second tag data read from the cache memory to the first tag data received from the cache controller with the first read request, and if the second tag data matches the first tag data, initiate an action with respect to the first cache line in the cache memory.

公开(公告)号：US11526445B2

公开(公告)日：2022-12-13

申请号：US16868088

申请日：2020-05-06

Applicant: Rambus Inc.

Inventor： Collins Williams ,  Michael Miller ,  Kenneth Wright

IPC: G06F12/08 ,  G06F12/0815 ,  G11C14/00

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.

公开(公告)号：US10031677B1

公开(公告)日：2018-07-24

申请号：US14883155

申请日：2015-10-14

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/0802

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.