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    MULTI-DIE MEMORY DEVICE
    13.
    发明申请
    MULTI-DIE MEMORY DEVICE 审中-公开

    公开(公告)号：US20200321047A1

    公开(公告)日：2020-10-08

    申请号：US16823122

    申请日：2020-03-18

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ming Li

    IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406

    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

    Multi-die memory device
    14.
    发明授权
    Multi-die memory device 有权

    公开(公告)号：US10607691B2

    公开(公告)日：2020-03-31

    申请号：US16211966

    申请日：2018-12-06

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ming Li

    IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406 ,  H01L23/00

    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

    Multi-die memory device
    15.
    发明授权
    Multi-die memory device 有权

    公开(公告)号：US10157660B2

    公开(公告)日：2018-12-18

    申请号：US15809925

    申请日：2017-11-10

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ming Li

    IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/406 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  H01L23/00

    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

    METHOD AND APPARATUS TO IMPROVE CONNECTION PITCH IN DIE-TO-WAFER BONDING
    18.
    发明申请
    METHOD AND APPARATUS TO IMPROVE CONNECTION PITCH IN DIE-TO-WAFER BONDING 有权

    公开(公告)号：US20220108964A1

    公开(公告)日：2022-04-07

    申请号：US17493264

    申请日：2021-10-04

    Applicant: Rambus Inc.

    Inventor： Dongyun Lee ,  Ming Li

    IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66 ,  G11C29/12

    Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor die having a first bonding surface that is formed with a first set of contacts patterned with a first connection pitch. A second semiconductor die has a second bonding surface that is formed with a second set of contacts patterned with a second connection pitch. The second set of contacts are further patterned with a paired offset. The second semiconductor die is bonded to the first semiconductor die such that the first set of contacts is disposed in opposed electrical engagement with at least a portion of the second set of contacts.

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