Simplified method to reduce or eliminate STI oxide divots
    11.
    发明授权
    Simplified method to reduce or eliminate STI oxide divots 失效
    简化方法来减少或消除STI氧化层

    公开(公告)号:US06432797B1

    公开(公告)日:2002-08-13

    申请号:US09768487

    申请日:2001-01-25

    IPC分类号: H01L2176

    摘要: A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench. The oxide layer is planarized to the semiconductor substrate wherein the nitrogen-rich oxide layer is planarized more slowly than the oxide layer resulting in a portion of the oxide layer remaining overlying the trench after the oxide layer overlying the semiconductor substrate has been removed wherein the portion of the oxide layer remaining provides a smooth transition between the shallow trench isolation and the active areas completing the formation of shallow trench isolation in the fabrication of an integrated circuit device.

    摘要翻译: 描述了形成浅沟槽隔离的方法,其中在隔离和有源区的边缘处的氧化物凹陷被减少或消除。 将沟槽蚀刻到半导体衬底中。 沉积在半导体衬底上并填充沟槽的氧化物层。 将氮原子注入到覆盖沟槽的氧化物层中。 将衬底退火,由此在覆盖沟槽的氧化物层的表面上形成一层富氮氧化物。 氧化物层平坦化到半导体衬底,其中富氧氧化物层平坦化比氧化物层缓慢,导致一部分氧化物层保留在沟槽上方,在氧化物层覆盖半导体衬底之后,其中部分 剩余的氧化物层在浅沟槽隔离和有源区域之间提供平滑的过渡,从而在集成电路器件的制造中完成浅沟槽隔离的形成。

    Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application

    公开(公告)号:US06399471B1

    公开(公告)日:2002-06-04

    申请号:US09783379

    申请日:2001-02-15

    IPC分类号: H01L2144

    摘要: A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

    Low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer
    16.
    发明授权
    Low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer 失效
    在绝缘层上使用选择性硅外延生长(SEG)的低泄漏DRAM结构

    公开(公告)号:US06384437B1

    公开(公告)日:2002-05-07

    申请号:US09963411

    申请日:2001-09-27

    IPC分类号: H01L27148

    CPC分类号: H01L27/10873 H01L27/10808

    摘要: Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance. This self-aligning method also increases memory cell density, and is integratable into current DRAM processes to reduce cost.

    摘要翻译: 使用在存储器单元(器件)区域上的绝缘层上的选择性硅外延生长来实现低电流泄漏DRAM结构。 也用作应力释放层的绝缘层和Si 3 N 4硬掩模被图案化以在存储器单元区域上留下部分。 在衬底中蚀刻浅沟槽,并填充有CVD氧化物,其被抛光回硬掩模以在存储器单元区域周围形成浅沟槽隔离(STI)。 选择性地去除硬掩模,以在STI暴露下面的绝缘层的存储单元区域上对准STI中形成凹槽。 在绝缘层中蚀刻开口以提供硅种子表面,从该晶种表面生长在凹陷内的绝缘层上延伸的选择性外延层。 在外延层上生长栅极氧化物之后,可以在外延层上形成FET和DRAM电容器。 外延层下方的绝缘层大大降低了电容器的漏电流,提高了DRAM器件性能。 这种自对准方法也增加了存储单元密度,并且可以集成到当前的DRAM工艺中以降低成本。

    Method to reduce compressive stress in the silicon substrate during silicidation
    17.
    发明授权
    Method to reduce compressive stress in the silicon substrate during silicidation 失效
    降低硅衬底中压缩应力的方法

    公开(公告)号:US06284610B1

    公开(公告)日:2001-09-04

    申请号:US09666315

    申请日:2000-09-21

    IPC分类号: H01L21336

    摘要: A method for siliciding source/drain junctions is described wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A gate electrode and associated source/drain extensions are provided in and on a semiconductor substrate. A buffer oxide layer is deposited overlying the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. The polysilicon layer will form the source/drain junctions and silicon source. The source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during the siliciding.

    摘要翻译: 描述了用于硅化源极/漏极结的方法,其中通过在硅化物和硅之间插入缓冲层来避免下面的硅的压缩应力。 栅极电极和相关的源极/漏极延伸部设置在半导体衬底中和半导体衬底上。 沉积在半导体衬底和栅电极上的缓冲氧化层。 堆叠在缓冲氧化物层上的多晶硅层。 多晶硅层将形成源极/漏极结和硅源。 源极/漏极结是硅化的,由此缓冲氧化物层在硅化期间提供压缩应力释放。

    Effective retardation of fluorine radical attack on metal lines via use of silicon rich oxide spacers
    18.
    发明授权
    Effective retardation of fluorine radical attack on metal lines via use of silicon rich oxide spacers 失效
    通过使用富硅氧化物间隔物有效延缓金属线上的氟自由基攻击

    公开(公告)号:US06376360B1

    公开(公告)日:2002-04-23

    申请号:US09641390

    申请日:2000-08-18

    IPC分类号: H01L214763

    CPC分类号: H01L21/76829 H01L21/76885

    摘要: A process for forming metal structures, encapsulated in silicon rich oxide, (SRO), shapes and layers, needed to protect the metal structures from the corrosive effects of fluorine radicals, present in low k, fluorinated silica glass, (FSG), which in turn is formed in the spaces between metal structures, has been developed. The process features initial formation of the metal structures, capped with an overlying SRO shape. This is followed by the formation of SRO spacers on the sides of the SRO capped, metal structures. Another thin, conformal SRO layer is then deposited to insure encapsulation of the metal structures, however still leaving adequate space between the SRO encapsulated metal structures for the low k FSG layer, needed to limit capacitance and improve device performance.

    摘要翻译: 存在于低k,氟化石英玻璃(FSG)中的形成金属结构的方法,该方法封装在富硅氧化物(SRO),形状和层中,以保护金属结构免受氟自由基的腐蚀作用。 在金属结构之间的空间中形成转弯,已经开发出来。 该工艺特征是初始形成金属结构,上覆SRO形状。 随后在SRO封盖的金属结构的侧面上形成SRO间隔物。 然后沉积另一薄的共形SRO层以确保金属结构的封装,然而仍然在限制电容和提高器件性能所需的低k FSG层的SRO封装的金属结构之间留下足够的空间。

    Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer
    19.
    发明授权
    Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer 失效
    在绝缘层上制造使用选择性硅外延生长(SEG)的低泄漏DRAM结构的方法

    公开(公告)号:US06319772B1

    公开(公告)日:2001-11-20

    申请号:US09697946

    申请日:2000-10-30

    IPC分类号: H01L218242

    CPC分类号: H01L27/10873 H01L27/10808

    摘要: Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance. This self-aligning method also increases memory cell density, and is integratable into current DRAM processes to reduce cost.

    摘要翻译: 使用在存储器单元(器件)区域上的绝缘层上的选择性硅外延生长来实现低电流泄漏DRAM结构。 也用作应力释放层的绝缘层和Si 3 N 4硬掩模被图案化以在存储器单元区域上留下部分。 在衬底中蚀刻浅沟槽,并填充有CVD氧化物,其被抛光回硬掩模以在存储器单元区域周围形成浅沟槽隔离(STI)。 选择性地去除硬掩模,以在STI暴露下面的绝缘层的存储单元区域上对准STI中形成凹槽。 在绝缘层中蚀刻开口以提供硅种子表面,从该晶种表面生长在凹陷内的绝缘层上延伸的选择性外延层。 在外延层上生长栅极氧化物之后,可以在外延层上形成FET和DRAM电容器。 外延层下方的绝缘层大大降低了电容器的漏电流,提高了DRAM器件性能。 这种自对准方法也增加了存储单元密度,并且可以集成到当前的DRAM工艺中以降低成本。

    Method to fabricate elevated source/drain structures in MOS transistors
    20.
    发明授权
    Method to fabricate elevated source/drain structures in MOS transistors 失效
    在MOS晶体管中制造升高的源极/漏极结构的方法

    公开(公告)号:US06727151B2

    公开(公告)日:2004-04-27

    申请号:US10213562

    申请日:2002-08-07

    IPC分类号: H01L21336

    摘要: A method for forming a MOSFET having an elevated source/drain structure is described. A sacrificial oxide layer is provided on a substrate. A polish stop layer is deposited overlying the sacrificial oxide layer. An oxide layer is deposited overlying the polish stop layer. An opening is formed through the oxide layer and the polish stop layer to the sacrificial oxide layer. First polysilicon spacers are formed on sidewalls of the opening wherein the first polysilicon spacers form an elevated source/drain structure. Second polysilicon spacers are formed on the first polysilicon spacers. The oxide layer and sacrificial oxide layer exposed within the opening are removed. An epitaxial silicon layer is grown within the opening. A gate dielectric layer is formed within the opening overlying the second polysilicon spacers and the epitaxial silicon layer. A gate material layer is deposited within the opening. The gate material layer, first polysilicon spacers and second polysilicon spacers are polished back to the polish stop layer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.

    摘要翻译: 描述了一种形成具有升高的源极/漏极结构的MOSFET的方法。 牺牲氧化物层设置在基板上。 抛光停止层沉积在牺牲氧化物层上。 沉积在抛光停止层上的氧化物层。 通过氧化物层和抛光停止层形成到牺牲氧化物层的开口。 第一多晶硅间隔物形成在开口的侧壁上,其中第一多晶硅间隔物形成升高的源极/漏极结构。 在第一多晶硅间隔物上形成第二多晶硅间隔物。 去除暴露在开口内的氧化物层和牺牲氧化物层。 在开口内生长外延硅层。 在覆盖第二多晶硅间隔物和外延硅层的开口内形成栅介质层。 栅极材料层沉积在开口内。 栅极材料层,第一多晶硅间隔物和第二多晶硅间隔物被抛光回到抛光停止层,从而在集成电路器件的制造中完成形成具有升高的源极/漏极结构的MOSFET。