公开(公告)号：US20140198116A1

公开(公告)日：2014-07-17

申请号：US13977261

申请日：2011-12-28

申请人： Bryan E. Veal ,  Travis T. Schluessler ,  Murali Ramadoss ,  Balaji Vembu

发明人： Bryan E. Veal ,  Travis T. Schluessler ,  Murali Ramadoss ,  Balaji Vembu

IPC分类号： G06T1/60

CPC分类号： G06T1/60 ,  G11C16/349

摘要： Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.

摘要翻译： 描述了在具有某些类型的非易失性存储器的图形子系统中增加易失性存储器的方法和装置。 在一个实施例中，包括将一个或多个静态或近静态图形资源存储在非易失性随机存取存储器（NVRAM）中。 NVRAM可直接由图形处理器使用，至少使用内存存储和加载命令。 该方法还包括执行图形应用的图形处理器。 图形处理器使用存储器加载命令来发送对应于存储在NVRAM中的至少一个静态或近静态图形资源的地址的请求。 该方法还包括响应于存储器加载命令将所请求的图形资源从NVRAM直接加载到图形处理器的高速缓存中。

公开(公告)号：US08646052B2

公开(公告)日：2014-02-04

申请号：US12059972

申请日：2008-03-31

申请人： Balaji Vembu ,  Nitin Sarangdhar ,  Vedvyas Shanbhogue

发明人： Balaji Vembu ,  Nitin Sarangdhar ,  Vedvyas Shanbhogue

IPC分类号： H04L29/06

CPC分类号： G06F21/606 ,  G06F21/10 ,  G06F21/84 ,  G06F2221/0735

摘要： In some embodiments, the invention involves securing sensitive data from mal-ware on a computing platform and, more specifically, to utilizing virtualization technology and protected audio video path technologies to prohibit a user environment from directly accessing unencrypted sensitive data. In an embodiment a service operating system (SOS) accesses sensitive data requested by an application running in a user environment virtual machine, or a capability operating system (COS). The SOS application encrypts the sensitive data before passing the data to the COS. The COS makes requests directly to a graphics engine which decrypts the data before displaying the sensitive data on a display monitor. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，本发明涉及在计算平台上确保来自恶意软件的敏感数据，更具体地说，涉及利用虚拟化技术和受保护的音频视频路径技术来禁止用户环境直接访问未加密的敏感数据。 在一个实施例中，服务操作系统（SOS）访问在用户环境虚拟机或能力操作系统（COS）中运行的应用所请求的敏感数据。 SOS应用程序在将数据传送到COS之前对敏感数据进行加密，COS会直接向图形引擎发出解密数据，然后在显示器上显示敏感数据。 描述和要求保护其他实施例。

公开(公告)号：US20090006690A1

公开(公告)日：2009-01-01

申请号：US11769576

申请日：2007-06-27

申请人： Balaji Vembu ,  Nitin Sarangdhar ,  Rajeev Nalawadi

发明人： Balaji Vembu ,  Nitin Sarangdhar ,  Rajeev Nalawadi

IPC分类号： G06F13/362

CPC分类号： G06F13/10

摘要： An apparatus, system, and method are disclosed. In one embodiment, the apparatus includes a virtualization engine on a computer platform. The virtualization engine can intercept multiple data transfer schedules from multiple virtual machines fetched from a memory by a physical Universal Serial Bus (USB) host controller on the computer platform. The virtualization engine also can merge the multiple fetched data transfer schedules into a merged data transfer schedule. The virtualization engine also can send the merged data transfer schedule to the physical USB host controller.

摘要翻译： 公开了一种装置，系统和方法。 在一个实施例中，该设备包括在计算机平台上的虚拟化引擎。 虚拟化引擎可以通过计算机平台上的物理通用串行总线（USB）主机控制器从多个虚拟机中捕获多个数据传输计划。 虚拟化引擎还可以将多个获取的数据传输计划合并到合并的数据传输计划中。 虚拟化引擎还可以将合并的数据传输计划发送到物理USB主机控制器。

公开(公告)号：US07340582B2

公开(公告)日：2008-03-04

申请号：US10956630

申请日：2004-09-30

申请人： Rajesh Madukkarumukumana ,  Ioannis Schoinas ,  Ku-jei King ,  Balaji Vembu ,  Gilbert Neiger ,  Richard Uhlig

发明人： Rajesh Madukkarumukumana ,  Ioannis Schoinas ,  Ku-jei King ,  Balaji Vembu ,  Gilbert Neiger ,  Richard Uhlig

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F11/0712 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0793 ,  G06F12/1081

摘要： An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

摘要翻译： 本发明的一个实施例是一种在直接存储器访问地址转换中处理故障的技术。 寄存器组存储由I / O设备请求的输入/输出（I / O）事务产生的故障的故障处理的全局控制或状态信息。 地址转换结构将访客物理地址转换为主机物理地址。 访客物理地址对应于I / O事务，并映射到域。 地址转换结构至少具有与域相关联的条目和用于故障处理的特定于域的控制信息。

公开(公告)号：US20070240018A1

公开(公告)日：2007-10-11

申请号：US11323297

申请日：2005-12-29

申请人： Rajeev Nalawadi ,  Balaji Vembu

发明人： Rajeev Nalawadi ,  Balaji Vembu

IPC分类号： G06F11/00

CPC分类号： G06F11/1438 ,  G06F11/1441

摘要： A device within a system, or an individual function of the device, may be reset to a known state while all other devices in the system or other functions of the device that are not being reset remain operational.

摘要翻译： 系统内的设备或设备的单独功能可以被重置为已知状态，而系统中的所有其他设备或未被重置的设备的其他功能保持工作。

公开(公告)号：US10649956B2

公开(公告)日：2020-05-12

申请号：US15477027

申请日：2017-04-01

申请人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

发明人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC分类号： G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/0831

摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180300238A1

公开(公告)日：2018-10-18

申请号：US15488637

申请日：2017-04-17

申请人： Balaji Vembu ,  Altug Koker ,  Josh B. Mastronarde ,  Nikos Kaburlasos ,  Abhishek R. Appu ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Pattabhiraman K ,  Kamal Sinha ,  Bhushan M. Borole ,  Wenyin Fu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

发明人： Balaji Vembu ,  Altug Koker ,  Josh B. Mastronarde ,  Nikos Kaburlasos ,  Abhishek R. Appu ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Pattabhiraman K ,  Kamal Sinha ,  Bhushan M. Borole ,  Wenyin Fu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC分类号： G06F12/06

摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

公开(公告)号：US20180285120A1

公开(公告)日：2018-10-04

申请号：US15477030

申请日：2017-04-01

申请人： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan Bhairavabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

发明人： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan Bhairavabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC分类号： G06F9/38 ,  G06F9/345 ,  G06F9/30 ,  G06F12/084 ,  G06T1/60 ,  G06T1/20 ,  G09G5/36

CPC分类号： G09G5/363 ,  G06F9/461 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/455 ,  G09G5/001 ,  G09G2340/02 ,  G09G2350/00 ,  G09G2352/00 ,  G09G2360/08 ,  G09G2360/121

摘要： A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US20150312524A1

公开(公告)日：2015-10-29

申请号：US14494707

申请日：2014-09-24

申请人： Balaji Vembu ,  Scott Janus ,  Changliang Wang

发明人： Balaji Vembu ,  Scott Janus ,  Changliang Wang

IPC分类号： H04N7/167

CPC分类号： H04N21/2347 ,  H04N21/4181 ,  H04N21/4405

摘要： Encryption and encoding of video and/or audio may be implemented on an integrated circuit before being transmitted wirelessly to a remote adapter for display.

摘要翻译： 视频和/或音频的加密和编码可以在被无线地传输到远程适配器进行显示之前在集成电路上实现。

公开(公告)号：US20150086012A1

公开(公告)日：2015-03-26

申请号：US14036263

申请日：2013-09-25

申请人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Prashant Dewan ,  David M. Durham ,  Balaji Vembu ,  Xiaozhu Kang ,  Scott Janus ,  Jason Martin ,  Vincent R. Scarlata

发明人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Prashant Dewan ,  David M. Durham ,  Balaji Vembu ,  Xiaozhu Kang ,  Scott Janus ,  Jason Martin ,  Vincent R. Scarlata

IPC分类号： H04N7/167

CPC分类号： G06F21/82 ,  G06F21/84 ,  G06F21/85 ,  H04N21/4122 ,  H04N21/4143 ,  H04N21/4367

摘要： Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a processing core communicatively coupled to the architecturally protected memory, the processing core comprising a processing logic configured to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory and preventing an unauthorized access to the architecturally protected memory; wherein the processing logic is further configured to provide a secure video output path by generating an output surface bitmap encrypted with a first encryption key and storing an encrypted first encryption key in an external memory, wherein the encrypted first encryption key is produced by encrypting the first encryption key with a second encryption key.

摘要翻译： 用于将输出表面位图安全传递到显示引擎的系统和方法。 一个示例处理系统包括：架构受保护的存储器; 以及处理核心，其通信地耦合到所述体系结构保护的存储器，所述处理核心包括处理逻辑，所述处理逻辑被配置为通过执行以下中的至少一个来实现架构保护的执行环境：执行驻留在架构保护的存储器中的指令， 建筑保护记忆; 其中所述处理逻辑还被配置为通过生成用第一加密密钥加密并将加密的第一加密密钥存储在外部存储器中的输出表面位图来提供安全视频输出路径，其中所述加密的第一加密密钥是通过加密所述第一加密密钥 具有第二加密密钥的加密密钥。