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    Memory devices and modules
    11.
    发明授权
    Memory devices and modules 有权

    公开(公告)号：US10002043B2

    公开(公告)日：2018-06-19

    申请号：US14678968

    申请日：2015-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chaohong Hu ,  Liang Yin ,  Hongzhong Zheng ,  Uksong Kang

    IPC: G06F11/00 ,  G06F11/10

    CPC classification number: G06F11/10 ,  G06F11/1008 ,  G06F11/1076

    Abstract: A memory device includes a memory, a data interface, an error interface and a controller. The data interface communicates data to and from the memory device through an external main memory path. The error interface communicates error information from the memory device through an external system control path and that is separate from the main memory path. The controller is coupled to the data interface, the error interface, and the memory. The controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the memory and generates corrected data by encoding data written to the memory and decoding data read from the memory, generates error information, transmits the corrected data through the data interface, and transmits the error information through the error interface. The ECC controller records the error information in response to the ECC engine.

    Memory devices and modules
    12.
    发明授权
    Memory devices and modules 有权

    公开(公告)号：US10002044B2

    公开(公告)日：2018-06-19

    申请号：US14678977

    申请日：2015-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chaohong Hu ,  Hongzhong Zheng ,  Uksong Kang ,  Zhan Ping

    IPC: G06F11/00 ,  G06F11/10

    CPC classification number: G06F11/10 ,  G06F11/1008 ,  G06F11/1076

    Abstract: A memory module includes a module error interface, a module data interface, and a plurality of memory device. The module error interface communicates error information a system control path. The module data interface communicates data to and from a main memory path that is separate from the system control path. Each memory device includes a device controller, a device error interface and a device data interface in which the error data interface is separate from the device data interface. Each device controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the corresponding memory device to generate corrected data, generate error information, communicate the error information through the device error interface to the module error interface, and communicate the corrected data through the device data interface to the module data interface. The ECC controller records the error information.

    VIRTUAL BUCKET MULTIPLE HASH TABLES FOR EFFICIENT MEMORY IN-LINE DEDUPLICATION APPLICATION
    15.
    发明申请
    VIRTUAL BUCKET MULTIPLE HASH TABLES FOR EFFICIENT MEMORY IN-LINE DEDUPLICATION APPLICATION 审中-公开

    公开(公告)号：US20170286005A1

    公开(公告)日：2017-10-05

    申请号：US15162517

    申请日：2016-05-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Frederic Sala ,  Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu ,  Mu-Tien Chang

    IPC: G06F3/06 ,  G06F12/10

    CPC classification number: G06F12/0864 ,  G06F12/0223 ,  G06F2212/1016 ,  G06F2212/1044

    Abstract: A method of deduplicating memory in a memory module includes identifying a hash table array including hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying a plurality of virtual buckets each including some of the physical buckets, and each sharing at least one of the physical buckets with another of the virtual buckets, hashing a block of data according to a corresponding one of the hash functions to produce a hash value, determining whether an intended physical bucket has available space for the block of data according to the hash value, and determining whether a near-location physical bucket has available space for the block of data when the intended physical bucket does not have available space, the near-location physical bucket being in a same one of the virtual buckets as the intended physical bucket.

    DEDUPE DRAM SYSTEM ALGORITHM ARCHITECTURE
    16.
    发明申请
    DEDUPE DRAM SYSTEM ALGORITHM ARCHITECTURE 有权

    公开(公告)号：US20170286004A1

    公开(公告)日：2017-10-05

    申请号：US15162512

    申请日：2016-05-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chaohong Hu ,  Hongzhong Zheng ,  Krishna Malladi ,  Bob Brennan

    IPC: G06F3/06

    CPC classification number: G11C29/808 ,  G06F12/0802 ,  G11C29/74

    Abstract: A deduplication memory module, which is configured to internally perform memory deduplication, includes a hash table memory for storing multiple blocks of data in a hash table array including hash tables, each of the hash tables including physical buckets and a plurality of virtual buckets each including some of the physical buckets, each of the physical buckets including ways, an address lookup table memory (ALUTM) including a plurality of pointers indicating a location of each of the stored blocks of data in a corresponding one of the physical buckets, and a buffer memory for storing unique blocks of data not stored in the hash table memory when the hash table array is full, a processor, and memory, wherein the memory has stored thereon instructions that, when executed by the processor, cause the memory module to exchange data with an external system.

    Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application
    17.
    发明授权
    Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application 有权

    公开(公告)号：US10318434B2

    公开(公告)日：2019-06-11

    申请号：US15905746

    申请日：2018-02-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Frederic Sala ,  Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu ,  Mu-Tien Chang

    IPC: G06F12/10 ,  G06F12/1018 ,  G06F12/0802 ,  G11C29/00 ,  G06F3/06

    Abstract: A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.

    Completely utilizing hamming distance for SECDED based ECC DIMMs
    20.
    发明授权
    Completely utilizing hamming distance for SECDED based ECC DIMMs 有权

    公开(公告)号：US09754684B2

    公开(公告)日：2017-09-05

    申请号：US14640005

    申请日：2015-03-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chaohong Hu ,  Hongzhong Zheng ,  Prashant Jayaprakash Nair

    IPC: H03M13/00 ,  G11C29/52 ,  H03M13/19 ,  G06F11/10 ,  G11C29/04

    CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411 ,  H03M13/19

    Abstract: In an Error Correction Code (ECC)-based memory, a Single Error Correction Double Error Detection (SECDED) scheme is used with data aggregation to correct more than one error in a memory word received in a memory burst. By completely utilizing the Hamming distance of the SECDED (128,120) code, 8 ECC bits can potentially correct one error in 120 data bits. Each memory burst is effectively “expanded” from its actual 64 data bits to 120 data bits by “sharing” additional 56 data bits from all of the other related bursts. When a cache line of 512 bits is read, the SECDED (128,120) code is used in conjunction with all the received 64 ECC bits to correct more than one error in the actual 64 bits of data in a memory word. The data mapping of the present disclosure translates to a higher rate of error correction than the existing (72,64) SECDED code.

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