中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.025 seconds)

    Semiconductor memory device
    11.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11621264B2

    公开(公告)日：2023-04-04

    申请号：US16999378

    申请日：2020-08-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

    IPC: H01L27/102 ,  H01L29/24 ,  H01L29/66 ,  H01L29/87 ,  H01L29/74 ,  H01L27/108 ,  H01L27/06

    Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    12.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220223713A1

    公开(公告)日：2022-07-14

    申请号：US17702856

    申请日：2022-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Naoto Umezawa ,  Satoru Yamada ,  Junsoo Kim ,  Honglae Park ,  Chunhyung Chung

    IPC: H01L29/51 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

    Semiconductor memory devices
    13.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11355509B2

    公开(公告)日：2022-06-07

    申请号：US17000857

    申请日：2020-08-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  Hyeongsun Hong ,  Yoosang Hwang

    IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524 ,  G11C11/404 ,  G11C11/4097

    Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

    SEMICONDUCTOR MEMORY DEVICES
    15.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210249417A1

    公开(公告)日：2021-08-12

    申请号：US17240486

    申请日：2021-04-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

    Semiconductor memory devices
    16.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US10991699B2

    公开(公告)日：2021-04-27

    申请号：US16820006

    申请日：2020-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

    Semiconductor memory devices
    17.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US10784272B2

    公开(公告)日：2020-09-22

    申请号：US16027887

    申请日：2018-07-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

    IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524 ,  G11C11/404 ,  G11C11/4097

    Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

    Semiconductor device having buried gate structure and method of fabricating the same
    19.
    发明授权
    Semiconductor device having buried gate structure and method of fabricating the same 有权

    公开(公告)号：US10263084B2

    公开(公告)日：2019-04-16

    申请号：US15868620

    申请日：2018-01-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongjin Lee ,  Junsoo Kim ,  Moonyoung Jeong ,  Satoru Yamada ,  Dongsoo Woo ,  Jiyoung Kim

    IPC: H01L29/40 ,  H01L29/423 ,  H01L27/108 ,  H01L27/088

    Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

Patent Agency Ranking