公开(公告)号：US20190333872A1

公开(公告)日：2019-10-31

申请号：US16227919

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L23/00 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

公开(公告)号：US11791287B2

公开(公告)日：2023-10-17

申请号：US17462522

申请日：2021-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L23/00 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/562 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

公开(公告)号：US11145672B2

公开(公告)日：2021-10-12

申请号：US16706684

申请日：2019-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Boh Chang Kim ,  Chung Ki Min ,  Ji Hoon Park ,  Byung Kwan You

IPC: H01L27/11582 ,  H01L23/00 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/538 ,  H01L27/11531

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

公开(公告)号：US10903229B2

公开(公告)日：2021-01-26

申请号：US16162533

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Sung Hun Lee

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L29/423 ,  G11C7/18 ,  G11C8/14 ,  H01L27/1157 ,  G11C5/02

Abstract: A three-dimensional semiconductor memory device including a gate-stack structure on a base substrate, the gate-stack structure including gate electrodes stacked in a direction perpendicular to a surface of the base substrate and spaced apart from each other; a through region penetrating through the gate-stack structure and surrounded by the gate-stack structure; and first vertical channel structures and second vertical channel structures on both sides of the through region and penetrating through the gate-stack structure, wherein the through region is between the first vertical channel structures and the second vertical channel structures.

公开(公告)号：US11903206B2

公开(公告)日：2024-02-13

申请号：US17747174

申请日：2022-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Seon Ahn ,  Ji Sung Cheon ,  Young Jin Kwon ,  Seok Cheon Baek ,  Woong Seop Lee

IPC: H01L29/66 ,  H10B43/27 ,  H01L21/28 ,  H01L29/423 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L29/40117 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.

公开(公告)号：US11342351B2

公开(公告)日：2022-05-24

申请号：US16257357

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Seon Ahn ,  Ji Sung Cheon ,  Young Jin Kwon ,  Seok Cheon Baek ,  Woong Seop Lee

IPC: H01L23/528 ,  H01L27/11 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/28

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.

公开(公告)号：US11264401B2

公开(公告)日：2022-03-01

申请号：US16270570

申请日：2019-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyoung Kim ,  Kwang Soo Kim ,  Seok Cheon Baek ,  Geun Won Lim

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157

Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

公开(公告)号：US20210398915A1

公开(公告)日：2021-12-23

申请号：US17462522

申请日：2021-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L23/00 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

公开(公告)号：US11133267B2

公开(公告)日：2021-09-28

申请号：US16227919

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L27/11573 ,  H01L23/00 ,  H01L27/11582

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

公开(公告)号：US11004860B2

公开(公告)日：2021-05-11

申请号：US16733539

申请日：2020-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Geun Won Lim

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/11573 ,  H01L23/535 ,  H01L27/11582 ,  H01L21/28

Abstract: A method for fabricating a non-volatile memory device is provided. The method includes forming a channel hole and a first contact hole simultaneously, several times, in order to achieve a desired a high aspect ratio.