公开(公告)号：US20240074193A1

公开(公告)日：2024-02-29

申请号：US18210729

申请日：2023-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoon Kim ,  Doohyun Kim ,  Hyunju Kim ,  Heesuk Kim ,  Yejin Park ,  Jaehwang Sim ,  Jongseon Ahn

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a lower circuit pattern on a substrate, a common source plate (CSP) on the lower circuit pattern, a gate electrode structure including gate electrodes spaced apart from each other on the CSP in a first direction that is substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction that is substantially parallel to the upper surface of the substrate, a first insulation pattern structure on a portion of the CSP that is adjacent to the gate electrode structure in the second direction, and a first division pattern extending on the CSP in a third direction that is substantially parallel to the upper surface of the substrate and that crosses the second direction, the first division pattern extending through a portion of the gate electrode structure that is adjacent to the first insulation pattern structure.

公开(公告)号：US20240038659A1

公开(公告)日：2024-02-01

申请号：US18142872

申请日：2023-05-03

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Yejin Park ,  Seungyoon Kim ,  Jongseon Ahn ,  Heesuk Kim ,  Jaehwang Sim

IPC: H01L23/528 ,  H01L23/522 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B80/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B80/00 ,  H01L25/0652 ,  H01L2225/06541

Abstract: A semiconductor device includes a substrate; a conductive layer; and a contact plug connected to the conductive layer. The contact plug includes a first portion; and a second portion, sequentially stacked, wherein a width of an upper surface of the first portion is wider than a width of a lower surface of the second portion. The contact plug includes a barrier layer; a first conductive layer on the barrier layer; and a second conductive layer on the first conductive layer. The second conductive layer comprises voids. The barrier layer, the first conductive layer, and the second conductive layer extend continuously in the first and second portions. The barrier layer has a first thickness, the second conductive layer has a second thickness, equal to or greater than the first thickness, and the first conductive layer has a third thickness, equal to or greater than the second thickness.

公开(公告)号：US20240014134A1

公开(公告)日：2024-01-11

申请号：US18370913

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H01L23/528 ,  H10B43/40 ,  H01L23/522 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H10B43/40 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L25/0652 ,  H01L2225/06506

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US20230380164A1

公开(公告)日：2023-11-23

申请号：US18116434

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon Park ,  Inhwan Baek ,  Jaebok Baek ,  Jeehoon Han ,  Seungyoon Kim ,  Heesuk Kim ,  Byoungjae Park ,  Jongseon Ahn ,  Jumi Yun

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes, each having a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.