公开(公告)号：US09558993B2

公开(公告)日：2017-01-31

申请号：US14072882

申请日：2013-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehwang Sim ,  Jaeho Min ,  Jaehan Lee ,  Keonsoo Kim

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/308 ,  H01L23/528 ,  H01L27/115

CPC classification number: H01L21/76802 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A pattern structure in a semiconductor device includes an extending line and a pad connected with an end portion of the extending line. The pad may have a width that is larger than a width of the extending line. The pad includes a protruding portion extending from a lateral portion of the pad. The pattern structure may be formed by simplified processes and may be employed in various semiconductor devices requiring minute patterns and pads.

Abstract translation: 半导体器件中的图案结构包括延伸线和与延伸线的端部连接的焊盘。 垫可以具有大于延伸线的宽度的宽度。 垫包括从垫的侧部延伸的突出部分。 图案结构可以通过简化的工艺形成，并且可以用于需要微小图案和焊盘的各种半导体器件中。

公开(公告)号：US20240090219A1

公开(公告)日：2024-03-14

申请号：US18231284

申请日：2023-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongseon AHN ,  Seungyoon Kim ,  Heesuk Kim ,  Yejin Park ,  Jaehwang Sim

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: A vertical memory device includes: a lower pad pattern disposed on a substrate; a cell stack structure disposed on the lower pad pattern and including first insulation layers and gate patterns, wherein the cell stack structure has a stepped shape; a through cell contact including a first through portion and a first protrusion, wherein the first through portion passes through a portion of the cell stack structure, and wherein the first protrusion protrudes from the first through portion and contacts an uppermost gate pattern of the gate patterns; and a first insulation pattern at least partially surrounding a sidewall, of the first through portion, that is below the first protrusion, wherein the first insulation pattern is longer than the first protrusion in a horizontal direction from the first through portion, and wherein a vertical thickness of the first protrusion is greater than a vertical thickness of the uppermost gate pattern.

公开(公告)号：US20250087585A1

公开(公告)日：2025-03-13

申请号：US18731176

申请日：2024-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin Jung ,  Jaehwang Sim

IPC: H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a first word line having a first electrode portion and a first extension portion extending from the first electrode portion, a second word line having a second electrode portion disposed at a higher level than the first electrode portion and a second extension portion extending from the second electrode portion, a first vertical memory structure penetrating through the first and second electrode portions in a vertical direction, and a first interconnection structure electrically connected to the first extension portion. The first extension portion includes a first lower portion extending from the first electrode portion and a first plug portion extending upwardly from at least one side of the first lower portion and connected to the first interconnection structure. At least a portion of the first lower portion has a thickness greater than a thickness of the first electrode portion.

公开(公告)号：US20240074193A1

公开(公告)日：2024-02-29

申请号：US18210729

申请日：2023-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoon Kim ,  Doohyun Kim ,  Hyunju Kim ,  Heesuk Kim ,  Yejin Park ,  Jaehwang Sim ,  Jongseon Ahn

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a lower circuit pattern on a substrate, a common source plate (CSP) on the lower circuit pattern, a gate electrode structure including gate electrodes spaced apart from each other on the CSP in a first direction that is substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction that is substantially parallel to the upper surface of the substrate, a first insulation pattern structure on a portion of the CSP that is adjacent to the gate electrode structure in the second direction, and a first division pattern extending on the CSP in a third direction that is substantially parallel to the upper surface of the substrate and that crosses the second direction, the first division pattern extending through a portion of the gate electrode structure that is adjacent to the first insulation pattern structure.

公开(公告)号：US20240038659A1

公开(公告)日：2024-02-01

申请号：US18142872

申请日：2023-05-03

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Yejin Park ,  Seungyoon Kim ,  Jongseon Ahn ,  Heesuk Kim ,  Jaehwang Sim

IPC: H01L23/528 ,  H01L23/522 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B80/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B80/00 ,  H01L25/0652 ,  H01L2225/06541

Abstract: A semiconductor device includes a substrate; a conductive layer; and a contact plug connected to the conductive layer. The contact plug includes a first portion; and a second portion, sequentially stacked, wherein a width of an upper surface of the first portion is wider than a width of a lower surface of the second portion. The contact plug includes a barrier layer; a first conductive layer on the barrier layer; and a second conductive layer on the first conductive layer. The second conductive layer comprises voids. The barrier layer, the first conductive layer, and the second conductive layer extend continuously in the first and second portions. The barrier layer has a first thickness, the second conductive layer has a second thickness, equal to or greater than the first thickness, and the first conductive layer has a third thickness, equal to or greater than the second thickness.