公开(公告)号：US20230298678A1

公开(公告)日：2023-09-21

申请号：US17699508

申请日：2022-03-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Dengtao Zhao

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/28 ,  G11C16/08

Abstract: A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.

公开(公告)号：US20230041476A1

公开(公告)日：2023-02-09

申请号：US17392500

申请日：2021-08-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Peter Rabkin ,  Henry Chin ,  Ken Oowada ,  Dengtao Zhao ,  Gerrit Jan Hemink

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

公开(公告)号：US20220383956A1

公开(公告)日：2022-12-01

申请号：US17329617

申请日：2021-05-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Dengtao Zhao

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/24

Abstract: A non-volatile memory system adjusts the speed of a memory operation for a subset of non-volatile memory cells. For example, during a GIDL based erase process, the GIDL generation can be dampened for a subset of memory cells (e.g., for a set of NAND strings, or one or more sub-blocks).

公开(公告)号：US20220375524A1

公开(公告)日：2022-11-24

申请号：US17323708

申请日：2021-05-18

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Ravi Kumar ,  Chin-Yi Chen ,  Ryohei Shoji

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/34 ,  G11C16/04

Abstract: A nonvolatile memory control method includes a step of writing, repeatedly to a nonvolatile memory cells. The method continues with detecting when writing reaches a writing threshold value. Upon reaching the writing threshold, the method continues with driving a charge to at least one parasitic area intermediate at least two charge storage areas of the nonvolatile memory cells to improve data retention in at least one of the at least two charge storage areas of the nonvolatile memory cells.

公开(公告)号：US11244735B2

公开(公告)日：2022-02-08

申请号：US16793749

申请日：2020-02-18

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/26

Abstract: A method for memory program verification includes performing a write operation on memory cells of a memory device. The method also includes identifying memory strings associated with respective memory cells of the memory cells. The method also includes identifying a first memory string of the memory strings. The method also includes disabling a portion of a write verification for the first memory string. The method also includes enabling the portion of the write verification for other memory strings of the memory strings. The method also includes performing at least the portion of the write verification operation on write verification enabled memory strings.

公开(公告)号：US20210407603A1

公开(公告)日：2021-12-30

申请号：US16915663

申请日：2020-06-29

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Dengtao Zhao ,  Huai-Yuan Tseng

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C11/56

Abstract: An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the program verify operation being applied to multiple tiers, wherein the first voltage level is less than the second voltage level. In embodiments, less than all of the tiers, e.g., two or four tiers, can be used in the program verify to represent all of the tires

公开(公告)号：US20210202011A1

公开(公告)日：2021-07-01

申请号：US16729951

申请日：2019-12-30

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Jiahui Yuan ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/04 ,  G11C11/56

Abstract: Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations.

公开(公告)号：US20210134369A1

公开(公告)日：2021-05-06

申请号：US16668675

申请日：2019-10-30

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/24 ,  G11C11/4074 ,  G11C11/409

Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the fist memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.

公开(公告)号：US10580504B2

公开(公告)日：2020-03-03

申请号：US16002836

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Peng Zhang ,  Nan Lu ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C11/56

Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

公开(公告)号：US12148478B2

公开(公告)日：2024-11-19

申请号：US17952846

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Masaaki Higashitani ,  Abhijith Prakash ,  Dengtao Zhao

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L25/065

Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.