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    Three-valued programming mechanism for non-volatile memory structures
    12.
    发明授权
    Three-valued programming mechanism for non-volatile memory structures 有权

    公开(公告)号：US11488669B2

    公开(公告)日：2022-11-01

    申请号：US17136828

    申请日：2020-12-29

    Applicant: SanDisk Technologies LLC

    Inventor： Keiji Nose ,  Hiroki Yabe ,  Masahiro Kano ,  Yuki Fujita

    IPC: G11C7/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C16/08

    Abstract: A method for programming three page user data in a memory array of a non-volatile memory system, comprising converting each three-bit value data pattern of the user data into a representative pair of two-bit data values, simultaneously programming two single-state memory cells with a first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of two memory cell strings, and simultaneously programming two single-state memory cells with a second of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a second common word line of the two memory cell strings.

    Level shifter with improved negative voltage capability
    13.
    发明授权
    Level shifter with improved negative voltage capability 有权

    公开(公告)号：US11336283B1

    公开(公告)日：2022-05-17

    申请号：US17326487

    申请日：2021-05-21

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Hiroki Yabe

    IPC: H03K19/0185 ,  G11C16/00 ,  G11C16/08 ,  H03K3/356

    Abstract: A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first plurality of NMOS transistors in series with a first input node and a negative amplified voltage, and the second leg includes a second plurality of NMOS transistors in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.

    LOOP-DEPENDENT SWITCHING BETWEEN PROGRAM-VERIFY TECHNIQUES
    14.
    发明申请
    LOOP-DEPENDENT SWITCHING BETWEEN PROGRAM-VERIFY TECHNIQUES 有权

    公开(公告)号：US20210407604A1

    公开(公告)日：2021-12-30

    申请号：US16916367

    申请日：2020-06-30

    Applicant: SanDisk Technologies LLC

    Inventor： Hiroki Yabe

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/30 ,  G06F9/30

    Abstract: A storage device for verifying whether memory cells have been programmed. The storage device may be configured to use a verification technique, that is part of a set of verification techniques, to verify data states of a set of memory cells of a selected word line. The one or more verification techniques may be utilized based on an iteration of the verify operation that is to be performed. The storage device may be further configured to perform, using the verification technique, a next iteration of the program-verify operation to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next-iteration of the program-verify operation are to be repeated until the set of memory cells have been verified.

    Sense amplifier architecture for low supply voltage operations
    15.
    发明授权
    Sense amplifier architecture for low supply voltage operations 有权

    公开(公告)号：US11081167B1

    公开(公告)日：2021-08-03

    申请号：US16912716

    申请日：2020-06-26

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Hiroki Yabe ,  Koichiro Hayashi

    IPC: G11C11/4074 ,  G11C11/4091

    Abstract: Systems and methods for reducing the energy per bit of memory cell sensing operations, such as memory read operations, by dynamically adjusting the body effect of data latch transistors during the sensing operations are described. A significant component of the energy required to perform the memory cell sensing operations may correspond with the parasitic currents through low threshold voltage (VT) transistors of data latches within sense amplifier circuits. In order to reduce the energy per bit of the memory cell sensing operations while using a reduced supply voltage for the data latches, the body effect of a select number of the low VT transistors within the data latches may be dynamically adjusted such that the body effect is minimized or nonexistent during the latching of new data into the data latches and then increased after the new data has been latched within the data latches.

    NEGATIVE KICK ON BIT LINE CONTROL TRANSISTORS FOR FASTER BIT LINE SETTLING DURING SENSING
    16.
    发明申请
    NEGATIVE KICK ON BIT LINE CONTROL TRANSISTORS FOR FASTER BIT LINE SETTLING DURING SENSING 审中-公开

    公开(公告)号：US20200265880A1

    公开(公告)日：2020-08-20

    申请号：US16866051

    申请日：2020-05-04

    Applicant: SanDisk Technologies LLC

    Inventor： Hiroki Yabe

    IPC: G11C7/12 ,  G11C13/00 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C7/10

    Abstract: A memory device and associated techniques improve a settling time of bit lines in a memory device during a read or verify operation. Bit line control (BLC) transistors in the sense circuits are briefly turned off during a sensing process. After the read voltage on a selected word line is changed to a second word line level or higher, a control gate voltage of the BLC transistor is lowered, helping to inhibit a current flow from a sense circuit through a bit line when a voltage of the bit line is settling. The voltage of the bit line may be settling in response to a memory cell coupled to the selected word line undergoing a transition from off to on. A settling time of the bit line is shortened by stopping the current flow from the sense circuit. Transition of the memory cell from off to on is also improved.

    IR drop compensation for sensing memory
    17.
    发明授权
    IR drop compensation for sensing memory 有权

    公开(公告)号：US12040010B2

    公开(公告)日：2024-07-16

    申请号：US17725712

    申请日：2022-04-21

    Applicant: SanDisk Technologies LLC

    Inventor： Hiroki Yabe

    IPC: G11C16/26 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

    CPC classification number: G11C11/4091 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096

    Abstract: Technology is disclosed herein for sensing memory cells while compensating for resistance along an electrical pathway between a voltage driver and a control line connected to the memory cells. A control circuit provides a voltage from the voltage driver over a first electrical pathway to a control line in a first block and a second electrical pathway to a control line in a second block. The control circuit senses first memory cells in the first block and the second memory cells in the second block while compensating for a difference in resistance of the first and second electrical pathways. In one aspect, the control circuit discharges a first sense node for a different period of time than a second sense node to compensate for the difference in resistance. Compensating for the difference in resistance compensates for a different IR drop of the electrical pathways.

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