公开(公告)号：US10460816B2

公开(公告)日：2019-10-29

申请号：US15967572

申请日：2018-04-30

Applicant: SanDisk Technologies LLC

Inventor： Pitamber Shukla ,  Mohan Dunga ,  Anubhav Khandelwal

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G06F3/06 ,  G11C11/4074 ,  G11C29/52 ,  G11C16/04

Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

公开(公告)号：US10074440B2

公开(公告)日：2018-09-11

申请号：US15337522

申请日：2016-10-28

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Mohan Dunga ,  Changyuan Chen

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/28 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/3431 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3495

Abstract: An erase operation includes one or more erase depth checks to detect the occurrence of shallow erased memory cells at the end of an erase process. Memory cells are subjected to erase and erase verification until erase verification success is achieved. At the end of successful erase verification, a subset of memory cells is read to detect an erase depth or level of the memory cells. If the erase depth check indicates that the subset memory cells are in a shallow erased condition, additional erasing and verification is performed.

公开(公告)号：US20180122489A1

公开(公告)日：2018-05-03

申请号：US15337522

申请日：2016-10-28

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Mohan Dunga ,  Changyuan Chen

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/28 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/3431 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3495

Abstract: An erase operation includes one or more erase depth checks to detect the occurrence of shallow erased memory cells at the end of an erase process. Memory cells are subjected to erase and erase verification until erase verification success is achieved. At the end of successful erase verification, a subset of memory cells is read to detect an erase depth or level of the memory cells. If the erase depth check indicates that the subset memory cells are in a shallow erased condition, additional erasing and verification is performed.

公开(公告)号：US11508654B2

公开(公告)日：2022-11-22

申请号：US16886702

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/115 ,  H01L27/06 ,  H01L23/00 ,  H01L49/02 ,  H01L27/11582

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

公开(公告)号：US11251191B2

公开(公告)日：2022-02-15

申请号：US16231760

申请日：2018-12-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lishan Weng ,  Fumiaki Toyama ,  Mohan Dunga

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, where each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, drain regions contacting an upper end of a respective one of the vertical semiconductor channels, first contact via structures directly contacting a first subset of the drain regions and each having a first horizontal cross-sectional area, and second contact via structures directly contacting a second subset of the drain regions and each having a second horizontal cross-sectional area that is greater than the first horizontal cross-sectional area.

公开(公告)号：US10984876B2

公开(公告)日：2021-04-20

申请号：US16445367

申请日：2019-06-19

Applicant: SanDisk Technologies LLC

Inventor： Piyush Dak ,  Mohan Dunga ,  Chao Qin ,  Muhammad Masuduzzaman ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.

公开(公告)号：US20200035313A1

公开(公告)日：2020-01-30

申请号：US16591210

申请日：2019-10-02

Applicant: Sandisk Technologies LLC

Inventor： Pitamber Shukla ,  Mohan Dunga ,  Anubhav Khandelwal

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G06F3/06 ,  G11C11/4074 ,  G11C29/52

Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

公开(公告)号：US10978145B2

公开(公告)日：2021-04-13

申请号：US16540862

申请日：2019-08-14

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Peter Rabkin ,  Mohan Dunga ,  Gerrit Jan Hemink ,  Changyuan Chen

IPC: G11C11/56 ,  G11C11/408 ,  G11C11/407 ,  G11C11/406 ,  G11C11/4074

Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.

公开(公告)号：US10825827B2

公开(公告)日：2020-11-03

申请号：US16141149

申请日：2018-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mohan Dunga ,  James Kai ,  Venkatesh P. Ramachandra ,  Piyush Dak ,  Luisa Lin ,  Masaaki Higashitani

IPC: H01L21/00 ,  H01L27/11582 ,  H01L27/11573 ,  G11C7/10 ,  G11C16/10 ,  G11C16/28 ,  H01L27/1157

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.

公开(公告)号：US10714169B1

公开(公告)日：2020-07-14

申请号：US16437355

申请日：2019-06-11

Applicant: SanDisk Technologies LLC

Inventor： Phil Reusswig ,  Pitamber Shukla ,  Sarath Puthenthermadam ,  Mohan Dunga ,  Sahil Sharma ,  Rohit Sehgal ,  Niles Yang

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.