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公开(公告)号：US10727825B2
公开(公告)日：2020-07-28
申请号：US15626627
申请日：2017-06-19
Applicant: SanDisk Technologies LLC
Inventor： Shiv Harit Mathur
Abstract: A circuit system may include a first stage circuit configured to generate two pairs of signals in response to an input signal. The circuit system may also include a second stage circuit that is configured to combine a first signal of a first pair with a first signal of a second pair to generate a first combined signal, and to combine a second signal of the first pair with a second signal of the second pair to generate a second combined signal. Transistors of the second stage circuit may be sized in relation to transition timings of the first and second pairs of signals such that skew and duty cycle distortion is minimized between the first and second combined signals.
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Patent Agency Ranking
公开(公告)号：US20180302074A1
公开(公告)日：2018-10-18
申请号：US15626627
申请日：2017-06-19
Applicant: SanDisk Technologies LLC
Inventor： Shiv Harit Mathur
Abstract: A circuit system may include a first stage circuit configured to generate two pairs of signals in response to an input signal. The circuit system may also include a second stage circuit that is configured to combine a first signal of a first pair with a first signal of a second pair to generate a first combined signal, and to combine a second signal of the first pair with a second signal of the second pair to generate a second combined signal. Transistors of the second stage circuit may be sized in relation to transition timings of the first and second pairs of signals such that skew and duty cycle distortion is minimized between the first and second combined signals.
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公开(公告)号：US20180123570A1
公开(公告)日：2018-05-03
申请号：US15858070
申请日：2017-12-29
Applicant: SanDisk Technologies LLC
Inventor： Shiv Harit Mathur
CPC classification number: H03K3/353 , G06F13/385 , H03K5/13 , H03K2005/00019
Abstract: A clock-receiving system may receive a host clock signal on a communications bus from a clock-sending system. Circuitry of a critical path of the clock-receiving system may communicate the clock signal to a multiplexer configured directly behind output driver circuitry. Core logic circuitry and data path circuitry may communicate pairs of phase-shifted data signals to the multiplexer. The multiplexer may use the clock signal and the pairs of phase-shifted data signals to generate an output pair of data signals, and send the output pair of data signals to the output driver circuitry. In turn, the output driver circuitry may generate an output data signal for communication on the communications bus. The clock-receiving system may enable the critical path and use the multiplexer to generate the output data signal when in a low operating voltage mode.
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公开(公告)号：US20230402107A1
公开(公告)日：2023-12-14
申请号：US17835324
申请日：2022-06-08
Applicant: SanDisk Technologies LLC
Inventor： Nitin Gupta , Shiv Harit Mathur , Ramakrishnan Subramanian , Dmitry Vaysman
CPC classification number: G11C16/30 , G11C11/1697
Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.
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公开(公告)号：US11803207B1
公开(公告)日：2023-10-31
申请号：US17733662
申请日：2022-04-29
Applicant: SanDisk Technologies LLC
Inventor： Shiv Harit Mathur , Avinash Pandit
Abstract: Systems and methods disclosed herein provide for an improved glitch-free clock multiplexer exhibiting noise insensitivity with reduced power consumption and reduced physical area on a chip. The embodiments disclosed herein operate without any need of a reference clock. Due to which, clock interchangeability is possible at any point of time. An example glitch-free clock multiplexing according to the embodiments disclosed herein utilize a plurality of clock path circuits, each corresponding to a clock. The clock path circuits are activated responsive to a system startup signal. Based on a clock selection, the embodiments herein deactivate clock path circuits for unselected clocks and, dependent on the deactivation of the unselected clock path circuits, activate clock path circuits of any selected clocks.
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公开(公告)号：US11210241B1
公开(公告)日：2021-12-28
申请号：US17068957
申请日：2020-10-13
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Nitin Gupta , Ashish Savadia , Jayanth Thimmaiah , Ramakrishnan Subramanian , Rampraveen Somasundaram , Shiv Harit Mathur , Vinayak Ghatawade , Siddesh Darne , Venkatesh Ramachandra , Elkana Richter
Abstract: A data storage system includes a storage medium including plurality of memory cells, a storage controller in communication with the storage medium, an electrical interface circuitry configured to pass data via a channel disposed between the storage medium and the storage controller; and voltage training circuitry configured to train a high-level output voltage (VOH) for each of a plurality of data lines of the channel. Training the VOH includes, for each of the plurality of data lines of the channel, calibrating a pull-up driver of the storage controller against an on-die termination circuit of the storage medium, calibrating a pull-down driver of the storage controller against the pull-up driver of the storage controller, and calibrating an on-die termination circuit of the storage controller against a pull-up driver of the storage medium.
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