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公开(公告)号：US20240112735A1
公开(公告)日：2024-04-04
申请号：US17955878
申请日：2022-09-29
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Wei Cao , Jiacen Guo
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/10 , G11C16/24
Abstract: In a multi-tiered non-volatile memory structure that can perform operations on sub-blocks, performance of the different tiers/sub-blocks is made consistent by using different word line to word line pitches in the different tiers/sub-blocks.
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公开(公告)号：US11935593B2
公开(公告)日：2024-03-19
申请号：US17824143
申请日：2022-05-25
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Jiahui Yuan , Xiang Yang
CPC classification number: G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/28
Abstract: An apparatus includes a control circuit configured to connect to memory cells connected in series in NAND strings. Each NAND string includes a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines. The control circuit configured to apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation to program data memory cells. The control circuit is configured to apply a second dummy word line voltage to the one or more dummy word lines in a read operation to read the data memory cells.
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公开(公告)号：US20240079062A1
公开(公告)日：2024-03-07
申请号：US17903618
申请日：2022-09-06
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Han-Ping Chen , Henry Chin , Guirong Liang , Xiang Yang
CPC classification number: G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/3459
Abstract: The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.
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公开(公告)号：US20240055059A1
公开(公告)日：2024-02-15
申请号：US17884929
申请日：2022-08-10
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Dengtao Zhao , Xiang Yang
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/10
Abstract: Non-volatile memory cells are programmed by pre-charging channels of unselected non-volatile memory cells connected to a selected data word line, boosting the channels of unselected non-volatile memory cells connected to the selected data word line after the pre-charging and applying a program voltage pulse to selected non-volatile memory cells connected to the selected data word line while boosting. The pre-charging includes applying pre-charge voltages to one set of data word lines and dummy word line(s) as well as applying overdrive voltages to another set of data word lines connected to already programmed memory cells. At the end of the pre-charging, the dummy word lines are ramped down to a resting voltage prior to lowering the data word lines to one or more resting voltages.
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公开(公告)号：US11881266B2
公开(公告)日：2024-01-23
申请号：US17667169
申请日：2022-02-08
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Kou Tei , Ohwon Kwon
Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.
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Patent Agency Ranking
公开(公告)号：US20230410921A1
公开(公告)日：2023-12-21
申请号：US17845060
申请日：2022-06-21
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Deepanshu Dutta , Jiacen Guo , Takayuki Inoue , Hua-Ling Hsu
CPC classification number: G11C16/3454 , G11C16/102 , G11C16/26 , G11C7/1039
Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.
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公开(公告)号：US11837292B2
公开(公告)日：2023-12-05
申请号：US17561016
申请日：2021-12-23
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Xiang Yang
CPC classification number: G11C16/16 , G11C16/105 , G11C16/26
Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes. The memory cells are connected in series between a drain-side select gate transistor on a drain-side and connected to one of a plurality of bit lines and a source line on a source-side. A control means is configured to apply a first and a second select gate voltage to the drain-side select gate transistor while applying a predetermined source line voltage to the source line of selected ones of the memory holes in a predetermined grouping and a read level voltage to at least one of the word lines associated with the predetermined grouping. The control means counts the memory cells conducting during each of a first and a second read operation and adjusts the predetermined source line voltage accordingly.
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公开(公告)号：US20230386585A1
公开(公告)日：2023-11-30
申请号：US17828685
申请日：2022-05-31
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Xiang Yang , Xiaochen Zhu
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/26
Abstract: To save power during a read process, NAND strings of each sub-block of a block have independently controlled source side select lines connected to source side select gates and drain side select lines connected to drain side select gates so that NAND strings of unselected sub-blocks can float and not draw current. To prevent read disturb in NAND strings of unselected sub-blocks, after all word lines are raised to a pass gate voltage, unselected word lines nearby the selected word line are lowered to respective intermediate voltages while lowering the voltage on the selected word line in order to achieve a channel potential gradient in the floated NAND strings of the unselected sub-blocks that does not result in read disturb. Subsequently, the selected word line is raised to the appropriate read compare voltage so the selected memory cells can be sensed.
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公开(公告)号：US20230377657A1
公开(公告)日：2023-11-23
申请号：US17750938
申请日：2022-05-23
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Chin-Yi Chen , Deepanshu Dutta
CPC classification number: G11C16/102 , G11C16/26 , G11C16/08 , G11C16/3404 , G11C16/24
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.
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20.发明公开公开(公告)号：US20230343400A1
公开(公告)日：2023-10-26
申请号：US17724769
申请日：2022-04-20
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Xiang Yang , Abhijith Prakash
CPC classification number: G11C16/3427 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3459
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.
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