公开(公告)号：US20220344334A1

公开(公告)日：2022-10-27

申请号：US17762473

申请日：2020-09-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru OHSHITA ,  Hitoshi KUNITAKE ,  Kazuki TSUDA

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.

公开(公告)号：US20220320330A1

公开(公告)日：2022-10-06

申请号：US17615759

申请日：2020-05-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi KUNITAKE ,  Kazuaki OHSHIMA

IPC: H01L29/786 ,  H03F1/56 ,  H03H7/38

Abstract: A matching circuit which can handle a plurality of frequencies is provided. The matching circuit includes a transistor and an inductor. The matching circuit uses capacitance formed between a gate and a source/drain (referred to as capacitance Cgsd below) of the transistor as a condenser. The capacitance Cgsd changes with the voltage of the gate with respect to the source (referred to as voltage Vgs below). The transistor included in the matching circuit is an OS transistor including a metal oxide in a channel formation region. The OS transistor features larger variation in capacitance Cgsd with respect to the voltage Vgs than the MOSFET that uses silicon, which enables the matching circuit to handle alternating-current signals in a wide frequency range.

公开(公告)号：US20220285560A1

公开(公告)日：2022-09-08

申请号：US17679413

申请日：2022-02-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Yasuhiro JINBO ,  Naoki OKUNO ,  Masahiro TAKAHASHI ,  Tomonori NAKAYAMA

IPC: H01L29/786 ,  G09G3/32

Abstract: A transistor whose characteristic degradation due to stray light is small is provided. The transistor includes a first insulator, a second insulator over the first insulator, a metal oxide over the second insulator, a first and a second conductor over the metal oxide, a third insulator over the first insulator, the second insulator, the metal oxide, the first conductor, and the second conductor, a fourth insulator over the metal oxide, a fifth insulator over the fourth insulator, and a third conductor over the fifth insulator. The third insulator has an opening to overlap with a region between the first conductor and the second conductor. The fourth insulator, the fifth insulator, and the third conductor are positioned in the opening. The metal oxide has a bandgap greater than or equal to 3.3 eV. The transistor has Vsh higher than or equal to −0.3 V.

公开(公告)号：US20220208248A1

公开(公告)日：2022-06-30

申请号：US17600379

申请日：2020-04-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi KUNITAKE ,  Yuto YAKUBO ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Tatsuya ONUKI

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/00

Abstract: A memory device includes m memory cell blocks, m×(k+1) word lines, n bit lines, and a word line driver circuit (m, k, and n are each an integer greater than or equal to 1). The memory cell block includes memory cells of (k+1) rows×n columns, and each of the memory cells is electrically connected to a word line and a bit line. The word line driver circuit has a function of outputting signals to m×k word lines that are selected from m×(k+1) word lines by using a switch transistor, and selection information is written to a gate of the switch transistor by using a transistor having a low off-state current. The memory cells of k rows×n columns included in the memory cell block are normal memory cells, and each of the memory cell blocks includes redundant memory cells of one row×n columns.

公开(公告)号：US20220035980A1

公开(公告)日：2022-02-03

申请号：US17299654

申请日：2019-11-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi KUNITAKE ,  Kazuki TSUDA ,  Tatsuki KOSHIDA ,  Takeya HIROSE ,  Tomoaki ATSUMI

IPC: G06F30/367

Abstract: A transistor model that achieves precise approximation of transistor electrical characteristics is provided. The transistor model is a field-effect transistor model. A first capacitor is provided between a gate and a source. A second capacitor is provided between the gate and a drain. Each of the first capacitor and the second capacitor is a non-linear capacitor whose capacitance value is determined depending on a gate voltage. The first capacitor may be composed of a plurality of variable capacitors. The second capacitor may be composed of a plurality of variable capacitors. When CV characteristics of the first capacitor and CV characteristics of the second capacitor are adjusted, more precise simulation data is obtained.

公开(公告)号：US20210367078A1

公开(公告)日：2021-11-25

申请号：US16975309

申请日：2019-02-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE ,  Yoko TSUKAMOTO

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66

Abstract: A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, abnormality in shape, or dielectric breakdown is inhibited is provided.
The semiconductor device includes a first region and a second region over the same plane. The first region includes a transistor. The second region includes a dummy transistor. The transistor includes a first wiring layer, a semiconductor layer including an oxide and provided above the first wiring layer, a second wiring layer provided above the semiconductor layer, and a third wiring layer provided above the second wiring layer. The dummy transistor has the same area as one or more selected from the first wiring layer, the second wiring layer, the semiconductor layer, and the third wiring layer.

公开(公告)号：US20250133824A1

公开(公告)日：2025-04-24

申请号：US18834712

申请日：2023-01-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO ,  Shunpei YAMAZAKI

IPC: H10D86/40 ,  H10D30/67 ,  H10D64/68

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. First to second transistors share a first metal oxide over a first insulator and a first conductor over the first metal oxide; the first transistor includes a second conductor and a second insulator which are over the first metal oxide and a third conductor over the second insulator; the second transistor includes a fourth conductor and a third insulator which are over the first metal oxide and a fifth conductor over the third insulator; a side surface of the first insulator includes a portion in contact with the fourth conductor; an end portion of the fourth conductor includes a portion positioned outward from an end portion of the first insulator; the second insulator is positioned between the first conductor and the second conductor; the metal oxide and the third conductor overlap with each other with the second insulator therebetween; the third insulator is positioned between the first conductor and the fourth conductor; and the metal oxide and the fifth conductor overlap with each other with the third insulator therebetween.

公开(公告)号：US20250048676A1

公开(公告)日：2025-02-06

申请号：US18713288

申请日：2022-11-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Ryota HODO ,  Satoru SAITO ,  Hitoshi KUNITAKE ,  Shunpei YAMAZAKI ,  Masahiro WAKUDA ,  Toshiki HAMADA

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof are provided. A semiconductor device includes a metal oxide, a first conductor and a second conductor over the metal oxide, a first insulator positioned over the metal oxide and between the first conductor and the second conductor, a second insulator over the first insulator, a third insulator over the second insulator, a third conductor over the third insulator, a fourth insulator positioned between the first conductor and the first insulator, and a fifth insulator positioned between the second conductor and the first insulator. The first insulator is in contact with the top surface and the side surface of the metal oxide, and oxygen is less likely to pass through the first insulator than the second insulator. The first conductor, the second conductor, the fourth insulator, and the fifth insulator contain the same metal element. In a cross-sectional view in a channel length direction, a distance from the first conductor to the first insulator is greater than or equal to a thickness of the first insulator and less than or equal to a distance from the third conductor to the metal oxide.

公开(公告)号：US20250008721A1

公开(公告)日：2025-01-02

申请号：US18706096

申请日：2022-10-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hitoshi KUNITAKE ,  Rihito WADA ,  Kiyoshi KATO ,  Tatsuya ONUKI

IPC: H10B12/00

Abstract: A small semiconductor device is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a p-channel first transistor containing silicon in a channel formation region. The second layer includes an n-channel second transistor containing a metal oxide in a channel formation region. The first transistor and the second transistor form a CMOS circuit. A channel length of the first transistor is longer than a channel length of the second transistor.

公开(公告)号：US20240260257A1

公开(公告)日：2024-08-01

申请号：US18559083

申请日：2022-04-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Yuki ITO

IPC: H10B12/00 ,  H01L29/786

CPC classification number: H10B12/50 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device that can be subjected to multipoint measurement is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a first multiplexer, a second multiplexer, m (m is an integer of 1 or more) analog switches electrically connected to the first multiplexer, and n (n is an integer of 1 or more) analog switches electrically connected to the second multiplexer. The second layer includes m×n transistors. Each of the m analog switches is electrically connected to n transistors, and each of the n analog switches is electrically connected to m transistors.