公开(公告)号：US20140302639A1

公开(公告)日：2014-10-09

申请号：US14311924

申请日：2014-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideki UOCHI ,  Daisuke KAWAE

IPC: H01L27/12

CPC classification number: H01L27/127 ,  G02F1/13454 ,  G02F1/13458 ,  G02F2001/13629 ,  H01L27/1225 ,  H01L29/7869

Abstract: To reduce adverse effects on actual operation and to reduce adverse effects of noise. A structure including an electrode, a wiring electrically connected to the electrode, an oxide semiconductor layer overlapping with the electrode in a plane view, an insulating layer provided between the electrode and the oxide semiconductor layer in a cross-sectional view, and a functional circuit to which a signal is inputted from the electrode through the wiring and in which operation is controlled in accordance with the signal inputted. A capacitor is formed using an oxide semiconductor layer, an insulating layer, and a wiring or an electrode.

Abstract translation: 减少对实际运行的不利影响，减少噪音的不利影响。 包括电极，与电极电连接的布线，在俯视图中与电极重叠的氧化物半导体层，在截面图中设置在电极和氧化物半导体层之间的绝缘层的结构，以及功能电路 通过布线从电极输入信号，并根据输入的信号控制操作。 使用氧化物半导体层，绝缘层，布线或电极形成电容器。

公开(公告)号：US20240234310A1

公开(公告)日：2024-07-11

申请号：US18560959

申请日：2022-05-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Kazuki TSUDA ,  Kouhei TOYOTAKA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU ,  Hideki UOCHI

IPC: H01L23/528 ,  H01L29/24

CPC classification number: H01L23/528 ,  H01L29/24

Abstract: A novel semiconductor device is provided. In reservoir computing using an input layer, a reservoir layer, and an output layer, variation in threshold voltage between transistors is used as a weight used for product arithmetic processing. Two transistors are provided in one product arithmetic circuit and data u is supplied to gates of the two transistors. Drain current of each of the transistors is determined by the data u and the threshold voltage of the transistor. The difference between the drain currents corresponds to a product arithmetic result. The difference between the drain currents is converted into voltage to be output. A plurality of product arithmetic circuits are connected in parallel to form a product-sum arithmetic circuit.

公开(公告)号：US20230290789A1

公开(公告)日：2023-09-14

申请号：US18133086

申请日：2023-04-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: H01L27/12 ,  G02F1/1362 ,  H01L27/02 ,  H01L29/786 ,  H10K59/131 ,  H10K59/121

CPC classification number: H01L27/1225 ,  G02F1/136204 ,  G02F1/136286 ,  H01L27/124 ,  H01L27/0266 ,  H01L29/7869 ,  H10K59/131 ,  H10K59/1213

Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

公开(公告)号：US20220285556A1

公开(公告)日：2022-09-08

申请号：US17749363

申请日：2022-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masahiro TAKAHASHI ,  Hideyuki KISHIDA ,  Akiharu MIYANAGA ,  Junpei SUGAO ,  Hideki UOCHI ,  Yasuo NAKAMURA

IPC: H01L29/786 ,  H01L21/768 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/24 ,  H01L29/423

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

公开(公告)号：US20210356784A1

公开(公告)日：2021-11-18

申请号：US17386849

申请日：2021-07-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke KUBOTA ,  Hideki UOCHI

IPC: G02F1/1347 ,  G02F1/1362 ,  H01L27/32 ,  G02F1/1333

Abstract: A highly reliable display device is provided. In a flexible display device including at least a first display region and a second display region, at least a portion of a wiring provided in the first display region or the second display region has a meandering shape or a chain-like shape. Since the wiring has a meandering shape or a chain-like shape, a short-circuit, a disconnection, or the like of the wiring due to curving or bending of the display device does not occur easily. The wiring having a meandering shape or a chain-like shape can prevent defective operation, lowered reliability, or the like of the display device.

公开(公告)号：US20210327916A1

公开(公告)日：2021-10-21

申请号：US17365174

申请日：2021-07-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: H01L27/12 ,  G02F1/1362 ,  H01L27/02 ,  H01L29/786 ,  H01L27/32

Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

公开(公告)号：US20200111913A1

公开(公告)日：2020-04-09

申请号：US16600375

申请日：2019-10-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masahiro TAKAHASHI ,  Hideyuki KISHIDA ,  Akiharu MIYANAGA ,  Junpei SUGAO ,  Hideki UOCHI ,  Yasuo NAKAMURA

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/24 ,  H01L29/66 ,  H01L21/768 ,  H01L21/324 ,  H01L21/02 ,  H01L27/12 ,  H01L29/49 ,  H01L29/45

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

公开(公告)号：US20180203312A1

公开(公告)日：2018-07-19

申请号：US15915663

申请日：2018-03-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: G02F1/1362 ,  H01L27/12 ,  H01L33/00 ,  H01L27/02

CPC classification number: G02F1/136204 ,  H01L27/0248 ,  H01L27/1225 ,  H01L27/124 ,  H01L33/0041 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In order to take advantage of the properties of a display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area are necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer over the gate insulating film; a channel protective layer covering a region which overlaps with a channel formation region of the first oxide semiconductor layer; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and over the first oxide semiconductor layer. The gate electrode is connected to a scan line or a signal line, the first wiring layer or the second wiring layer is directly connected to the gate electrode.

公开(公告)号：US20180047852A1

公开(公告)日：2018-02-15

申请号：US15728591

申请日：2017-10-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masahiro TAKAHASHI ,  Hideyuki KISHIDA ,  Akiharu MIYANAGA ,  Yasuo NAKAMURA ,  Junpei SUGAO ,  Hideki UOCHI

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/78669 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78678 ,  H01L29/7869

Abstract: It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed.

公开(公告)号：US20170285425A1

公开(公告)日：2017-10-05

申请号：US15623838

申请日：2017-06-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: G02F1/1362 ,  H01L33/00 ,  H01L27/02 ,  H01L27/12

CPC classification number: G02F1/136204 ,  H01L27/0248 ,  H01L27/1225 ,  H01L27/124 ,  H01L33/0041 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In order to take advantage of the properties of a display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area are necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer over the gate insulating film; a channel protective layer covering a region which overlaps with a channel formation region of the first oxide semiconductor layer; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and over the first oxide semiconductor layer. The gate electrode is connected to a scan line or a signal line, the first wiring layer or the second wiring layer is directly connected to the gate electrode.