公开(公告)号：US20180114844A1

公开(公告)日：2018-04-26

申请号：US15841891

申请日：2017-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Daisuke KAWAE

IPC: H01L29/417 ,  H01L51/10 ,  H01L51/05 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H01L21/02

CPC classification number: H01L29/41733 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0508 ,  H01L51/0512 ,  H01L51/0545 ,  H01L51/105

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

公开(公告)号：US20130217191A1

公开(公告)日：2013-08-22

申请号：US13845443

申请日：2013-03-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yoshiyuki KUROKAWA ,  Yasuhiro JINBO ,  Satoshi KOBAYASHI ,  Daisuke KAWAE

IPC: H01L29/66

CPC classification number: H01L29/66765 ,  H01L28/40 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/78696

Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and methods for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a pair of buffer layers formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the pair of buffer layers, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes the impurity element which serves as a donor.

公开(公告)号：US20160343740A1

公开(公告)日：2016-11-24

申请号：US15228457

申请日：2016-08-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiaki OIKAWA ,  Hotaka MARUYAMA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/32 ,  H01L27/15 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L27/1225 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/156 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/24 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.

公开(公告)号：US20140339556A1

公开(公告)日：2014-11-20

申请号：US14451680

申请日：2014-08-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Daisuke KAWAE

IPC: H01L29/417 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0508 ,  H01L51/0512 ,  H01L51/0545 ,  H01L51/105

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract translation: 下栅极薄膜晶体管中的源电极和漏电极之间可能发生的电场浓度被放宽并且抑制了开关特性的劣化的结构及其制造方法。 制造在源电极和漏电极上设置氧化物半导体层的底栅薄膜晶体管，与氧化物半导体层接触的源电极的侧表面的角度和角度;角度和角度; 与氧化物半导体层接触的漏电极的侧面的两个面积分别被设定为大于或等于20°且小于90°，​​使得从上边缘到下边缘的距离 每个电极的侧表面增加。

公开(公告)号：US20130214270A1

公开(公告)日：2013-08-22

申请号：US13763874

申请日：2013-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Daisuke KAWAE

IPC: H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0508 ,  H01L51/0512 ,  H01L51/0545 ,  H01L51/105

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract translation: 下栅极薄膜晶体管中的源电极和漏电极之间可能发生的电场浓度被放宽并且抑制了开关特性的劣化的结构及其制造方法。 制造在栅极和漏极之上设置氧化物半导体层的底栅极薄膜晶体管，并且与氧化物半导体层接触的源电极的侧表面的角度θ1和侧面的角度θ2 与氧化物半导体层接触的漏电极的表面各自被设定为大于或等于20°且小于90°，​​使得从每个的侧表面的顶边到底边的距离 电极增加。

公开(公告)号：US20140302639A1

公开(公告)日：2014-10-09

申请号：US14311924

申请日：2014-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideki UOCHI ,  Daisuke KAWAE

IPC: H01L27/12

CPC classification number: H01L27/127 ,  G02F1/13454 ,  G02F1/13458 ,  G02F2001/13629 ,  H01L27/1225 ,  H01L29/7869

Abstract: To reduce adverse effects on actual operation and to reduce adverse effects of noise. A structure including an electrode, a wiring electrically connected to the electrode, an oxide semiconductor layer overlapping with the electrode in a plane view, an insulating layer provided between the electrode and the oxide semiconductor layer in a cross-sectional view, and a functional circuit to which a signal is inputted from the electrode through the wiring and in which operation is controlled in accordance with the signal inputted. A capacitor is formed using an oxide semiconductor layer, an insulating layer, and a wiring or an electrode.

Abstract translation: 减少对实际运行的不利影响，减少噪音的不利影响。 包括电极，与电极电连接的布线，在俯视图中与电极重叠的氧化物半导体层，在截面图中设置在电极和氧化物半导体层之间的绝缘层的结构，以及功能电路 通过布线从电极输入信号，并根据输入的信号控制操作。 使用氧化物半导体层，绝缘层，布线或电极形成电容器。

公开(公告)号：US20140127874A1

公开(公告)日：2014-05-08

申请号：US14151046

申请日：2014-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Daisuke KAWAE

IPC: H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/1033 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/78696

Abstract: A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ∈r/d is greater than or equal to 0.08 (nm−1) and less than or equal to 7.9 (nm−1) when the relative permittivity of a material used for the gate insulating layer is ∈r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.

Abstract translation: 一种半导体器件，包括氧化物半导体层，与氧化物半导体层电连接的源电极和漏电极，覆盖氧化物半导体层的栅绝缘层，源电极和漏电极以及栅电极 提供栅极绝缘层。 氧化物半导体层的厚度大于或等于1nm且小于或等于10nm。 当栅极绝缘层用的材料的相对介电常数为（0.65）〜（0.85））时，栅极绝缘层满足关系式∈r/ d大于等于0.08（nm-1）且小于等于7.9（nm-1） ∈r，栅极绝缘层的厚度为d。 源电极和漏极之间的距离大于或等于10nm且小于或等于1μm。

公开(公告)号：US20160204270A1

公开(公告)日：2016-07-14

申请号：US15074287

申请日：2016-03-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Daisuke KAWAE

IPC: H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0508 ,  H01L51/0512 ,  H01L51/0545 ,  H01L51/105

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract translation: 下栅极薄膜晶体管中的源电极和漏电极之间可能发生的电场浓度被放宽并且抑制了开关特性的劣化的结构及其制造方法。 制造在源电极和漏电极上设置氧化物半导体层的底栅薄膜晶体管，与氧化物半导体层接触的源电极的侧表面的角度和角度;角度和角度; 与氧化物半导体层接触的漏电极的侧面的两个面积分别被设定为大于或等于20°且小于90°，​​使得从上边缘到下边缘的距离 每个电极的侧表面增加。

公开(公告)号：US20160064572A1

公开(公告)日：2016-03-03

申请号：US14934387

申请日：2015-11-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Daisuke KAWAE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L29/78693 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

Abstract translation: 对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤， 其中形成沟道区。 将形成在氧化物半导体层中的沟道的长度设定为0.2μm〜3.0μm，将氧化物半导体层和栅极绝缘层的厚度设定为15nm〜30nm，包括20nm〜50nm， 或分别为15nm〜100nm，10nm〜20nm。 因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。

公开(公告)号：US20190074361A1

公开(公告)日：2019-03-07

申请号：US16180580

申请日：2018-11-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Daisuke KAWAE

IPC: H01L29/417 ,  H01L51/10 ,  H01L51/05 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H01L21/02

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.