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公开(公告)号：US10734977B1
公开(公告)日：2020-08-04
申请号：US16379874
申请日：2019-04-10
Applicant: Silicon Laboratories Inc.
Inventor： Wenhuan Yu , Abdulkerim L. Coban
Abstract: In one form, an analog-to-digital converter (ADC) includes first and second ring-oscillator ADCs, a modulus subtractor, and a decimation filter. The first and second ring-oscillator ADCs are responsive to true and complement input voltages, respectively, have outputs for providing first and second digital phase signals, respectively, each having a first predetermined number of bits sampled at a first frequency. The modulus subtractor subtracts the second digital phase signal from the first digital phase signal to provide a phase difference signal. The decimation filter differentiates the phase difference signal at a second frequency lower than said the frequency to provide a frequency signal proportional to a differential voltage between the true input voltage and the complementary input voltage, and decimates the frequency signal to provide a digital code having a second predetermined number of bits greater than the first predetermined number of bits.
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公开(公告)号：US20170201282A1
公开(公告)日：2017-07-13
申请号：US15470989
申请日：2017-03-28
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban , Alessandro Piovaccari , Ramin K. Poorfard , James T. Kao
CPC classification number: H04B1/16 , H03G3/3068
Abstract: A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.
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公开(公告)号：US09491394B2
公开(公告)日：2016-11-08
申请号：US14254340
申请日：2014-04-16
Applicant: SILICON LABORATORIES INC.
Inventor： András Vince Horvath , Abdulkerim L. Coban , Pio Balmelli , Ramin Khoini-Poorfard , Alessandro Piovaccari
CPC classification number: H04N5/50 , H03J5/24 , H04L25/0292 , H04N5/165 , H04N5/455 , H04N21/42607
Abstract: In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.
Abstract translation: 在一个实施例中，内部缓冲器可以设置在集成电路（IC）内，以在开关的控制下将信号转换成经由IC的引脚输出的输出电流，该开关可以基于配置设置 IC，并且当IC耦合到外部驱动器电路时，可以选择性地将信号耦合到引脚。
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公开(公告)号：US09407276B1
公开(公告)日：2016-08-02
申请号：US14747057
申请日：2015-06-23
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban , Mustafa H. Koroglu
CPC classification number: H03M1/002 , H03M1/0626 , H03M1/1009 , H03M1/124 , H03M1/60
Abstract: In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value.
Abstract translation: 在一个实施例中，一种装置包括：第一压控振荡器（VCO）模数转换器（ADC）单元，用于接收差分模拟信号的第一部分，并将差分模拟信号的第一部分转换成第一数字 值; 第二VCO ADC单元，用于接收差分模拟信号的第二部分，并将差分模拟信号的第二部分转换为第二数字值; 组合器，用于从第一和第二数字值形成组合的数字信号; 一个抽取电路，用于接收组合的数字信号，并将组合的数字信号滤波成经滤波的组合数字信号; 以及抵消电路，用于至少部分地基于系数值接收经滤波的组合数字信号并产生失真消除的数字信号。
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15.发明申请INTEGRATED RECEIVER AND INTEGRATED CIRCUIT HAVING INTEGRATED INDUCTORS AND METHOD THEREFOR 有权具有集成电感器的集成接收器和集成电路及其方法公开(公告)号：US20150147992A1
公开(公告)日：2015-05-28
申请号：US14612346
申请日：2015-02-03
Applicant: Silicon Laboratories Inc.
Inventor： Ramin Khoini-Poorfard , Alessandro Piovaccari , Aslamali A. Rafi , Mustafa H. Koroglu , David S. Trager , Abdulkerim L. Coban
IPC: H04B1/28 , H04L27/148
Abstract: In one form, an integrated receiver includes a tracking bandpass filter, a tunable lowpass filter, and a mixer formed on a single integrated circuit chip. The tracking bandpass filter has an input for receiving a radio frequency (RF) input signal, and an output, and comprises a variable capacitor having a capacitance that varies in response to a bandpass frequency control signal, in parallel with an integrated inductor. The integrated inductor comprises a plurality of windings formed in a plurality of metal layers. The tunable lowpass filter has an input coupled to the output of the tracking bandpass filter, and an output and having a tuning input for receiving a cutoff frequency signal. The mixer has a signal input coupled to the output of the tunable lowpass filter, a local oscillator input for receiving a local oscillator signal, and a signal output for providing a converted RF signal.
Abstract translation: 在一种形式中，集成接收器包括跟踪带通滤波器，可调谐低通滤波器和形成在单个集成电路芯片上的混频器。 跟踪带通滤波器具有用于接收射频（RF）输入信号和输出的输入，并且包括与集成电感器并联的具有响应于带通频率控制信号而变化的电容的可变电容器。 集成电感器包括形成在多个金属层中的多个绕组。 可调谐低通滤波器具有耦合到跟踪带通滤波器的输出的输入端和输出端，并具有用于接收截止频率信号的调谐输入端。 混频器具有耦合到可调谐低通滤波器的输出的信号输入，用于接收本地振荡器信号的本地振荡器输入和用于提供经转换的RF信号的信号输出。
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Patent Agency Ranking
公开(公告)号：US08885106B2
公开(公告)日：2014-11-11
申请号：US13799384
申请日：2013-03-13
Applicant: Silicon Laboratories Inc.
Inventor： Mustafa H. Koroglu , Abdulkerim L. Coban
CPC classification number: H04N5/4401 , H04N5/455 , H04N5/50 , H04N21/4263 , H04N21/4382
Abstract: An apparatus includes a splitter to receive a radio frequency (RF) signal and to provide the RF signal to multiple channels of a tuner. Each channel may include an amplifier to amplify the RF signal, a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, where each of the channels is configured to receive a different LO signal, a filter to filter the downconverted second frequency signal, and a digitizer to digitize the downconverted second frequency signal. A clock generation circuit has multiple interpolative dividers and a frequency synthesizer to generate a reference clock signal. Each of the interpolative dividers is configured to receive the reference clock signal, generate a corresponding LO signal, and provide the corresponding LO signal to the mixer of at least one of the channels.
Abstract translation: 一种装置包括用于接收射频（RF）信号并将RF信号提供给调谐器的多个信道的分离器。 每个通道可以包括用于放大RF信号的放大器，使用本地振荡器（LO）信号将放大的RF信号下变频到第二频率信号的混频器，其中每个信道被配置为接收不同的LO信号，滤波器 对下变频的第二频率信号进行滤波，以及数字转换器，对下变频的第二频率信号进行数字化。 时钟发生电路具有多个内插分频器和频率合成器，以产生参考时钟信号。 每个内插分频器被配置为接收参考时钟信号，产生相应的LO信号，并将相应的LO信号提供给至少一个信道的混频器。
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公开(公告)号：US20140226074A1
公开(公告)日：2014-08-14
申请号：US14254340
申请日：2014-04-16
Applicant: SILICON LABORATORIES INC.
Inventor： András Vince Horvath , Abdulkerim L. Coban , Pio Balmelli , Ramin Khoini-Poorfard , Alessandro Piovaccari
CPC classification number: H04N5/50 , H03J5/24 , H04L25/0292 , H04N5/165 , H04N5/455 , H04N21/42607
Abstract: In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.
Abstract translation: 在一个实施例中，内部缓冲器可以设置在集成电路（IC）内，以在开关的控制下将信号转换成经由IC的引脚输出的输出电流，该开关可以基于配置设置 IC，并且当IC耦合到外部驱动器电路时，可以选择性地将信号耦合到引脚。
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公开(公告)号：US20250112658A1
公开(公告)日：2025-04-03
申请号：US18374843
申请日：2023-09-29
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban
IPC: H04B1/16
Abstract: A wideband power detector (peak or RMS) is placed in a base-band portion of a receiver chain implemented with a current mode RF front end. A differential transimpedance amplifier (TIA) includes a current sense circuit that replicates the input currents to the TIA as current sense output voltages without the current sense output voltages being affected by the filter characteristics of the TIA.
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19.发明公开公开(公告)号：US20240267005A1
公开(公告)日：2024-08-08
申请号：US18639872
申请日：2024-04-18
Applicant: Silicon Laboratories Inc.
Inventor： Rangakrishnan Srinivasan , Mustafa H. Koroglu , Zhongda Wang , Francesco Barale , Abdulkerim L. Coban , John M. Khoury , Sriharsha Vasadi , Michael S. Johnson , Vitor Pereira
CPC classification number: H03F1/26 , H03B5/04 , H03F1/30 , H03F3/245 , H03K5/00 , H03F2200/375 , H03K2005/00019
Abstract: A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to amplify the delayed oscillating signal for transmission sufficient to produce interference, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.
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20.发明授权公开(公告)号：US10469112B2
公开(公告)日：2019-11-05
申请号：US15609337
申请日：2017-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban
Abstract: In one example, a method includes: at a beginning of a packet communication, setting a maximum gain setting for a plurality of gain components of a receiver; and during a preamble portion of the packet communication, reducing a gain setting for one or more of the plurality of gain components in response to at least one of a first signal output by a first component of the receiver being greater than a first threshold and a second signal output by a second component of the receiver being greater than a second threshold.
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