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公开(公告)号：US20230318609A1
公开(公告)日：2023-10-05
申请号：US17709642
申请日：2022-03-31
Applicant: Silicon Laboratories Inc.
Inventor： Rangakrishnan Srinivasan , Zhongda Wang , Francesco Barale , Wenhuan Yu , Mustafa H. Koroglu , Yan Zhou , Terry L. Dickey
CPC classification number: H03L7/1075 , H04B1/40 , H03L7/099
Abstract: A phase-locked loop (PLL) that provides a local oscillator signal for a radio. An oscillator of the PLL supplies an oscillator output signal. Control logic receives a request to change the oscillator output signal to a new frequency and responds to the request by setting a first capacitor circuit of the oscillator to a first capacitance that corresponds to a predetermined frequency of the oscillator output signal. The control logic also responds to the request by setting one or more other capacitor circuits of the oscillator according to temperature and according to a frequency difference between the predetermined frequency and the new frequency. After responding to the request by setting the first capacitor circuit and the one or more other capacitor circuits, the PLL locks to the new frequency using a signal from the PLL loop filter to adjust another capacitor circuit in the oscillator.
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公开(公告)号：US10734977B1
公开(公告)日：2020-08-04
申请号：US16379874
申请日：2019-04-10
Applicant: Silicon Laboratories Inc.
Inventor： Wenhuan Yu , Abdulkerim L. Coban
Abstract: In one form, an analog-to-digital converter (ADC) includes first and second ring-oscillator ADCs, a modulus subtractor, and a decimation filter. The first and second ring-oscillator ADCs are responsive to true and complement input voltages, respectively, have outputs for providing first and second digital phase signals, respectively, each having a first predetermined number of bits sampled at a first frequency. The modulus subtractor subtracts the second digital phase signal from the first digital phase signal to provide a phase difference signal. The decimation filter differentiates the phase difference signal at a second frequency lower than said the frequency to provide a frequency signal proportional to a differential voltage between the true input voltage and the complementary input voltage, and decimates the frequency signal to provide a digital code having a second predetermined number of bits greater than the first predetermined number of bits.
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Patent Agency Ranking
公开(公告)号：US11699974B1
公开(公告)日：2023-07-11
申请号：US17853064
申请日：2022-06-29
Applicant: Silicon Laboratories Inc.
Inventor： Mohamed M. Elkholy , Mustafa Koroglu , Wenhuan Yu
Abstract: A frequency synthesizer on an integrated circuit provides a local oscillator (LO) signal for RF operations and also functions as an injection clock signal source during crystal oscillator startup. The integrated circuit goes into a sleep mode in which the crystal oscillator is off and responsive to a wakeup event the crystal oscillator starts up again using the injection clock signal sourced from the frequency synthesizer. Parameters that cause the injection clock signal to match the crystal oscillator frequency are stored. The frequency synthesizer includes a phase-locked loop having an LC oscillator. A digital to analog converter controls the LC oscillator during injection. During an initial power up of the integrated circuit, a PLL in the frequency synthesizer locks to the crystal oscillator frequency to determine the parameters to store for injection.
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公开(公告)号：US11973509B2
公开(公告)日：2024-04-30
申请号：US17709642
申请日：2022-03-31
Applicant: Silicon Laboratories Inc.
Inventor： Rangakrishnan Srinivasan , Zhongda Wang , Francesco Barale , Wenhuan Yu , Mustafa H. Koroglu , Yan Zhou , Terry L. Dickey
CPC classification number: H03L7/1075 , H03L7/099 , H04B1/40
Abstract: A phase-locked loop (PLL) that provides a local oscillator signal for a radio. An oscillator of the PLL supplies an oscillator output signal. Control logic receives a request to change the oscillator output signal to a new frequency and responds to the request by setting a first capacitor circuit of the oscillator to a first capacitance that corresponds to a predetermined frequency of the oscillator output signal. The control logic also responds to the request by setting one or more other capacitor circuits of the oscillator according to temperature and according to a frequency difference between the predetermined frequency and the new frequency. After responding to the request by setting the first capacitor circuit and the one or more other capacitor circuits, the PLL locks to the new frequency using a signal from the PLL loop filter to adjust another capacitor circuit in the oscillator.
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公开(公告)号：US10826501B1
公开(公告)日：2020-11-03
申请号：US16450083
申请日：2019-06-24
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban , Wenhuan Yu , Mustafa H. Koroglu
Abstract: A calibration operation adjusts a frequency of a ring oscillator to a desired frequency by adjusting programmable RC circuits in the stages of the ring oscillator. The programmable RC circuits have programmable capacitors, resistors, or both. The RC circuits account for most of the delay through the ring oscillator. Another circuit with its own RC time constant is calibrated based on the adjustments made to the RC circuits in the ring oscillator to achieve the desired frequency.
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公开(公告)号：US10523251B1
公开(公告)日：2019-12-31
申请号：US16156294
申请日：2018-10-10
Applicant: SILICON LABORATORIES INC.
Inventor： Abdulkerim L. Coban , Emmanuel Gautier , Fabrice Portier , Pascal Blouin , Wenhuan Yu
Abstract: A communications receiver with improved blocker performance including multiple gain tables selected based on a number of reductions or back offs from a maximum coarse gain setting. A receiver chain with multiple gain stages converts a received signal to a digital format, determines the power level of the received signal, and provides an overload indication. A first gain table maximizes SNR and SNDR for weak blockers and at least one additional gain table successively improves SNDR for stronger blockers. An AGC circuit initially sets the coarse gain setting to maximum, and backs off a number of coarse gain steps until the receiver chain is not overloaded. The number of back off steps is used to select a gain table, the power level is used to select an entry in the selected table, and the selected entry includes gain settings for the gain stages of the receiver chain.
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公开(公告)号：US09729162B1
公开(公告)日：2017-08-08
申请号：US15223310
申请日：2016-07-29
Applicant: SILICON LABORATORIES INC.
Inventor： Wenhuan Yu , Abdulkerim L. Coban
CPC classification number: H03M1/0617 , H03F3/45183 , H03F3/45475 , H03F3/45636 , H03F3/45659 , H03F2200/267 , H03F2203/45022 , H03F2203/45222 , H03F2203/45418 , H03F2203/45424 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45591 , H03H11/04 , H03H11/0422 , H03H11/1213 , H03K5/1252 , H03M1/00 , H03M1/12 , H03M1/145 , H03M1/502
Abstract: In one form, a signal chain circuit includes a signal chain processing circuit between an input for receiving a differential input signal having a first common-mode voltage, and an output for providing a differential output signal having a second, different common-mode voltage. It includes an amplifier with a differential output stage coupled to a differential input stage and having positive and negative output terminals forming its output, and positive and negative feedback terminals. The differential output stage provides a first voltage drop between the positive output terminal and the positive feedback terminal, and a second voltage drop between the negative output terminal and the negative feedback terminal. The common-mode feedback circuit regulates a common-mode voltage between the positive and negative feedback terminals to the second common-mode voltage. In another form, an analog-to-digital converter includes a range extending logic circuit to extend the range of a ring oscillator based analog-to-digital converter.
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