公开(公告)号：US20240040796A1

公开(公告)日：2024-02-01

申请号：US18484144

申请日：2023-10-10

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Jae Gil LEE

IPC: H10B51/20 ,  H01L29/78 ,  H01L29/792 ,  H01L29/66

CPC classification number: H10B51/20 ,  H01L29/78391 ,  H01L29/792 ,  H01L29/66833 ,  H01L29/6684

Abstract: A method of manufacturing a semiconductor device comprises: providing a substrate; forming a ferroelectric layer on the substrate; stacking two-dimensional conductive metal-organic frameworks that include cavities on the ferroelectric layer to form a metal-organic framework layer, the cavities of the conductive metal-organic frameworks being disposed to overlap with each other in a thickness direction of the metal-organic framework layer; disposing metal particles within the overlapping cavities to form a charge trap layer; forming a gate insulation layer on the charge trap layer; and forming a gate electrode layer on the gate insulation layer.

公开(公告)号：US20230099330A1

公开(公告)日：2023-03-30

申请号：US17674835

申请日：2022-02-17

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Jae Gil LEE

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a ferroelectric layer disposed on the substrate, a gate insulation layer disposed on the ferroelectric layer, metal particles disposed in the gate insulation layer, and a gate electrode layer disposed on the gate insulation layer.

公开(公告)号：US20230064803A1

公开(公告)日：2023-03-02

申请号：US17581575

申请日：2022-01-21

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Jae Gil LEE

IPC: H01L27/11597 ,  H01L29/78 ,  H01L29/66 ,  H01L29/792

Abstract: A semiconductor device includes a substrate, a ferroelectric layer disposed on the substrate in a vertical direction, a charge trap layer disposed on the ferroelectric layer, a gate insulation layer disposed on the charge trap layer, and a gate electrode layer disposed on the gate insulation layer. The charge trap layer includes a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

公开(公告)号：US20230030038A1

公开(公告)日：2023-02-02

申请号：US17964483

申请日：2022-10-12

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Hyangkeun YOO ,  Jae Hyun HAN

IPC: H01L45/00 ,  H01L27/24 ,  H01L27/11502

Abstract: A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.

公开(公告)号：US20220336533A1

公开(公告)日：2022-10-20

申请号：US17491916

申请日：2021-10-01

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE

IPC: H01L27/28 ,  H01L51/00 ,  H01L51/05

Abstract: A semiconductor device according to an embodiment of the present disclosure includes a substrate, a resistance change layer disposed on the substrate and including a plurality of carbon nanostructures, a channel layer disposed on the resistance change layer, a gate electrode layer disposed on the channel layer, and a source electrode layer and a drain electrode layer disposed to contact portions of the channel layer.

公开(公告)号：US20200212060A1

公开(公告)日：2020-07-02

申请号：US16558678

申请日：2019-09-03

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO ,  Ju Ry SONG ,  Se Ho LEE ,  Jae Gil LEE

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/267 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure.

公开(公告)号：US20240244826A1

公开(公告)日：2024-07-18

申请号：US18618805

申请日：2024-03-27

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Dong Ik SUH ,  Jae Gil LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/056 ,  H10B12/482

Abstract: A semiconductor device includes a substrate, a bit line conductive layer extending in a lateral direction substantially parallel to a surface of the substrate, a first insulation line structure extending in a second direction that is perpendicular to the first lateral direction and that is substantially parallel to the surface of the substrate, first and second channel structures that are disposed to respectively contact first and second sides of the first insulation line structure and that partially overlap with the bit line conductive layer, first and second gate dielectric layers respectively disposed over the substrate and on side surfaces of the first and second channel structures, and first and second gate line conductive layers extending in the second lateral direction over the substrate and covering at least a portion of each of the first and second gate dielectric layers, respectively.

公开(公告)号：US20220352461A1

公开(公告)日：2022-11-03

申请号：US17496971

申请日：2021-10-08

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Jae Hyun HAN ,  Jae Gil LEE

IPC: H01L45/00

Abstract: A semiconductor device according to an embodiment includes a substrate, a source electrode layer and a drain electrode layer that are disposed to be spaced apart from each other on the substrate, an active layer disposed on the substrate to contact the source electrode layer and the drain electrode layer, and a gate electrode layer disposed on the active layer. The active layer includes metal oxide capable of exsolving and reincorporating metal particles. The electrical resistance in the active layer is configured to be reversibly changed by exsolution and reincorporation of the metal particles.

公开(公告)号：US20220123021A1

公开(公告)日：2022-04-21

申请号：US17560248

申请日：2021-12-22

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO ,  Jae Gil LEE ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer.

公开(公告)号：US20220122980A1

公开(公告)日：2022-04-21

申请号：US17200057

申请日：2021-03-12

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Dong Ik SUH ,  Jae Gil LEE

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate, a bit line conductive layer disposed on the substrate and extending in a first lateral direction substantially parallel to a surface of the substrate, first and second channel structures disposed on the bit line conductive layer to be spaced apart from each other in the first lateral direction, first and second gate dielectric layers disposed on side surfaces of the first and second channel structures over the substrate, first and second gate line conductive layers disposed on the first and second gate dielectric layers, respectively, the first and second gate line conductive layers common to the first and second channel structures, respectively, and extending in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate, and first and second storage node electrode layers disposed over the first and second channel structures, respectively.