公开(公告)号：US10483255B2

公开(公告)日：2019-11-19

申请号：US16448241

申请日：2019-06-21

Applicant: Socionext Inc.

Inventor： Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/10 ,  H03K17/16 ,  H01L29/08 ,  H01L27/118 ,  H01L27/092 ,  H03K19/00 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L27/12 ,  H01L29/78

Abstract: A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.

公开(公告)号：US10373943B2

公开(公告)日：2019-08-06

申请号：US15953899

申请日：2018-04-16

Applicant: Socionext Inc.

Inventor： Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L23/528 ,  H03K17/16 ,  H01L27/088 ,  H03K19/00 ,  H01L27/118 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L27/12 ,  H01L29/78

Abstract: A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.

公开(公告)号：US09558801B2

公开(公告)日：2017-01-31

申请号：US14755935

申请日：2015-06-30

Applicant: SOCIONEXT INC.

Inventor： Hirotaka Takeno ,  Akio Yamamoto

IPC: G11C11/00 ,  G11C11/16 ,  G11C14/00 ,  H03K3/3562 ,  G11C13/00 ,  H03K19/18

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081 ,  G11C14/009 ,  H03K3/3562 ,  H03K19/18

Abstract: A data holding circuit includes: a latch circuit having a first terminal and a second terminal, a logical value held at the first terminal being changed according to a value to be held by the data holding circuit, and the second terminal holding an inverted logical value of the logical value held at the first terminal; and a storing circuit which stores the logical values held at the first terminal and the second terminal in response to a write signal, and sets the logical values held at the first terminal and the second terminal to the stored logical values in response to a read signal, wherein the storing circuit includes two Magnetic Tunnel Junction elements which are connected in series between the first terminal and the second terminal and in reverse directions to each other.

Abstract translation: 数据保持电路包括：具有第一端子和第二端子的锁存电路，保持在第一端子处的逻辑值根据由数据保持电路保持的值而改变，第二端子保持反相逻辑值 在第一个终端持有的逻辑价值; 以及存储电路，其响应于写信号存储保持在第一终端和第二终端的逻辑值，并且响应于读信号将保持在第一终端和第二终端的逻辑值设置为存储的逻辑值 其中，所述存储电路包括串联连接在所述第一端子和所述第二端子之间并且彼此相反方向的两个磁隧道结元件。

公开(公告)号：US12295168B2

公开(公告)日：2025-05-06

申请号：US18744087

申请日：2024-06-14

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L23/528 ,  H10D30/43 ,  H10D30/67 ,  H10D62/10 ,  H10D84/85

Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

公开(公告)号：US12283542B2

公开(公告)日：2025-04-22

申请号：US17577994

申请日：2022-01-18

Applicant: Socionext Inc.

Inventor： Hirotaka Takeno ,  Atsushi Okamoto ,  Toshio Hino

IPC: H01L23/528 ,  H01L23/522 ,  H10D89/10

Abstract: A semiconductor device includes first and second power supply lines formed in a first wiring layer and extending in a first direction; third and fourth power supply lines formed in a second wiring layer, extending in a second direction, and connected to the first and second power supply lines, respectively; a fifth power supply line formed in the first wiring layer; and a first power switch circuit including a transistor provided between the first and fifth power supply lines. The transistor overlaps at least one of the third and fourth power supply lines. The first power switch circuit includes first and second wirings formed in the second wiring layer, extending in the second direction, not overlapping the third and fourth power supply lines, and connected to a source of the transistor and the fifth power supply line, and to a drain and the third power supply line, respectively.

公开(公告)号：US12184282B2

公开(公告)日：2024-12-31

申请号：US17724247

申请日：2022-04-19

Applicant: Socionext Inc.

Inventor： Hirotaka Takeno ,  Atsushi Okamoto ,  Wenzhen Wang

IPC: H03K19/173 ,  H01L23/495 ,  H01L23/528 ,  H01L29/78

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

公开(公告)号：US12154904B2

公开(公告)日：2024-11-26

申请号：US17714683

申请日：2022-04-06

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Wenzhen Wang ,  Hirotaka Takeno

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.

公开(公告)号：US20190312024A1

公开(公告)日：2019-10-10

申请号：US16448241

申请日：2019-06-21

Applicant: Socionext Inc.

Inventor： Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/02 ,  H01L27/088 ,  H01L23/528 ,  H01L27/118 ,  H01L27/092 ,  H01L29/10 ,  H03K17/16 ,  H01L29/08 ,  H03K19/00 ,  H01L21/8238

Abstract: A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.

公开(公告)号：US12284828B2

公开(公告)日：2025-04-22

申请号：US17829341

申请日：2022-05-31

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H10D84/90

Abstract: A semiconductor device includes a first chip including a substrate and a first wiring layer formed on a first surface of the substrate; and a second wiring layer formed on a second surface of the substrate opposite to the first surface of the substrate. The second wiring layer includes a first power line to which a first power potential is applied; a second power line to which a second power potential is applied; a third power line to which a third power potential is applied; a first switch connected between the first power line and the second power line; and a second switch provided on one of the first power line or the third power line. The first chip includes a first circuit provided between the first power line and the third power line.

公开(公告)号：US12119301B2

公开(公告)日：2024-10-15

申请号：US17716299

申请日：2022-04-08

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Atsushi Okamoto ,  Hirotaka Takeno

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.