公开(公告)号：US20190244949A1

公开(公告)日：2019-08-08

申请号：US16386116

申请日：2019-04-16

Applicant: SOCIONEXT INC.

Inventor： Junji IWAHORI

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/0886 ,  H01L27/11803 ,  H01L2027/11875 ,  H01L2027/11879 ,  H01L2027/11881

Abstract: A semiconductor integrated circuit device includes a standard cell having a plurality of height regions. A plurality of partial circuits having an identical function and each operating in response to common signals S and NS are arranged in any one of the height regions. A metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits, and a metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits.

公开(公告)号：US20190198530A1

公开(公告)日：2019-06-27

申请号：US16287907

申请日：2019-02-27

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/0207 ,  H01L27/04 ,  H01L27/092 ,  H01L29/78 ,  H01L2027/11812 ,  H01L2027/11862 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/11892

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

公开(公告)号：US20240347460A1

公开(公告)日：2024-10-17

申请号：US18752353

申请日：2024-06-24

Applicant: Socionext Inc.

Inventor： Junji IWAHORI

IPC: H01L23/528 ,  H01L23/48 ,  H01L27/02

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L27/0207

Abstract: First and second semiconductor chips are stacked one upon the other with the back face of the first semiconductor chip opposed to the principal face of the second semiconductor chip. The first semiconductor chip includes: first and second power lines formed in a buried interconnect layer, extending in the X direction, and adjoining each other in the Y direction; first and second contacts provided between the first and second power lines and the chip back face; and a third contact provided between a signal line and the chip back face. The third contact has an overlap with the first power line in the Y direction and is at a position different from the positions of the first and second contacts in the X direction, in planar view.

公开(公告)号：US20230411396A1

公开(公告)日：2023-12-21

申请号：US18461371

申请日：2023-09-05

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/823871 ,  H01L21/823821 ,  H01L29/78 ,  H01L27/0629 ,  H01L27/0207 ,  H01L2027/11812 ,  H01L2027/11862 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/11892

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

公开(公告)号：US20230163133A1

公开(公告)日：2023-05-25

申请号：US18150501

申请日：2023-01-05

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L29/4238 ,  H01L29/1079 ,  H01L21/823828 ,  H01L29/775 ,  H01L29/0847 ,  B82Y10/00 ,  H01L29/42392 ,  H01L21/823821 ,  H01L29/0696 ,  H01L29/0673 ,  H01L27/0924 ,  H01L29/78696 ,  H01L27/0207 ,  H01L2027/11864 ,  H01L2027/11874

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US20220310658A1

公开(公告)日：2022-09-29

申请号：US17838895

申请日：2022-06-13

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

公开(公告)号：US20220216319A1

公开(公告)日：2022-07-07

申请号：US17706177

申请日：2022-03-28

Applicant: Socionext Inc.

Inventor： Junji IWAHORI

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

Abstract: In a p-type region, a nanosheet farthest from an n-type region has a face exposed from a first gate interconnect on the side away from the n-type region in the Y direction. In the n-type region, a nanosheet farthest from the p-type region has a face exposed from a second gate interconnect on the side away from the p-type region in the Y direction. In the p-type region, a nanosheet closest to the n-type region has a face exposed from the first gate interconnect on the side closer to the n-type region in the Y direction. In the n-type region, a nanosheet closest to the p-type region has a face exposed from the second gate interconnect on the side closer to the p-type region in the Y direction.

公开(公告)号：US20210028162A1

公开(公告)日：2021-01-28

申请号：US17069235

申请日：2020-10-13

Applicant: SOCIONEXT INC.

Inventor： Junji IWAHORI

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/118 ,  H01L21/822 ,  H01L21/82 ,  H01L27/04

Abstract: A semiconductor integrated circuit device includes a standard cell having a plurality of height regions. A plurality of partial circuits having an identical function and each operating in response to common signals S and NS are arranged in any one of the height regions. A metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits, and a metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits.

公开(公告)号：US20240363686A1

公开(公告)日：2024-10-31

申请号：US18767734

申请日：2024-07-09

Applicant: Socionext Inc.

Inventor： Junji IWAHORI

IPC: H01L29/06 ,  G11C11/412 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H10B10/00

CPC classification number: H01L29/0673 ,  G11C11/412 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H10B10/12 ,  H01L2027/11881

Abstract: A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P3 and N3, VDD is supplied to a pair of pads 22c, 22d and a gate interconnect 36c, and VSS is supplied to a pair of pads 27c, 27d and a gate interconnect 31c. Capacitances are produced between nanosheets 21c and the gate interconnect 31c and between nanosheets 26c and the gate interconnect 36c. The faces of the nanosheets 21c closer to the nanosheets 26c are exposed from the gate interconnect 31c, and the faces of the nanosheets 26c closer to the nanosheets 21c are exposed from the gate interconnect 36c.

公开(公告)号：US20240145390A1

公开(公告)日：2024-05-02

申请号：US18410874

申请日：2024-01-11

Applicant: SOCIONEXT INC.

Inventor： Hideyuki KOMURO ,  Junji IWAHORI

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L27/092

Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.