公开(公告)号：US20200295138A1

公开(公告)日：2020-09-17

申请号：US16086275

申请日：2017-03-31

Applicant: Soitec

Inventor： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

IPC: H01L29/161 ,  H01L23/00

Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

公开(公告)号：US20150056783A1

公开(公告)日：2015-02-26

申请号：US14334328

申请日：2014-10-03

Applicant: Soitec

Inventor： Sebastien Kerdiles ,  Daniel Delprat

IPC: H01L21/67 ,  H01L21/762

CPC classification number: H01L21/67132 ,  H01L21/02 ,  H01L21/187 ,  H01L21/76251

Abstract: A method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.

Abstract translation: 一种用于将具有第一表面的第一基底结合到具有第二表面的第二基底的方法。 该方法包括以下步骤：通过至少两个支撑点保持第一基板，将第一基板和第二基板定位成使得第一表面和第二表面彼此面对，使第一基板通过在至少一个压力点 并且两个支撑点朝向第二基板的应变，使变形的第一表面和第二表面接触，并逐渐释放应变以促进基板的接合，同时最小化或避免在基板之间捕获气泡。

公开(公告)号：US20230230874A1

公开(公告)日：2023-07-20

申请号：US18007145

申请日：2021-06-23

Applicant: Soitec

Inventor： Bruno Clemenceau ,  Ludovic Ecarnot ,  Aymen Ghorbel ,  Marcel Broekaart ,  Daniel Delprat ,  Séverin Rouchier ,  Stephane Thieffry ,  Carine Duret

IPC: H01L21/762 ,  H01L21/683 ,  H01L21/02

CPC classification number: H01L21/76254 ,  H01L21/6835 ,  H01L21/02274

Abstract: A method for transferring a thin layer onto a carrier substrate comprises preparing a carrier substrate using a preparation method involving supplying a base substrate having, on a main face, a charge-trapping layer and forming a dielectric layer having a thickness greater than 200 nm on the charge-trapping layer. Once the dielectric layer is formed, the ionized deposition and sputtering of the dielectric layer are simultaneously performed. The transfer method also comprises assembling, by way of molecular adhesion and with an unpolished free face of the dielectric layer, a donor substrate to the dielectric layer of the carrier substrate, the donor substrate having an embrittlement plane defining the thin layer. Finally, the method comprises splitting the donor substrate at the embrittlement plane to release the thin layer and to transfer it onto the carrier substrate.

公开(公告)号：US20210058058A1

公开(公告)日：2021-02-25

申请号：US17075465

申请日：2020-10-20

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H03H3/10

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US09293473B2

公开(公告)日：2016-03-22

申请号：US14612772

申请日：2015-02-03

Applicant: Soitec

Inventor： Patrick Reynaud ,  Sebastien Kerdiles ,  Daniel Delprat

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/76254 ,  H01L29/0649

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract translation: 一种具有降低的电损耗的绝缘体上半导体结构的制造方法，其包括由硅，氧化物层和半导体材料薄层制成的支撑衬底，以及在支撑衬底和氧化物层之间交错的多晶硅层 。 该方法包括能够在形成多晶硅层之前赋予支撑衬底高电阻率的处理，然后在不超过950℃的温度下在结构上进行至少一个长的热稳定化至少10分钟。

公开(公告)号：US20150171110A1

公开(公告)日：2015-06-18

申请号：US14612772

申请日：2015-02-03

Applicant: SOITEC

Inventor： Patrick Reynaud ,  Sebastien Kerdiles ,  Daniel Delprat

IPC: H01L27/12 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/76254 ,  H01L29/0649

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract translation: 一种具有降低的电损耗的绝缘体上半导体结构的制造方法，其包括由硅，氧化物层和半导体材料薄层制成的支撑衬底，以及在支撑衬底和氧化物层之间交错的多晶硅层 。 该方法包括能够在形成多晶硅层之前赋予支撑衬底高电阻率的处理，然后在不超过950℃的温度下在结构上进行至少一个长的热稳定化至少10分钟。

公开(公告)号：US11595020B2

公开(公告)日：2023-02-28

申请号：US16877309

申请日：2020-05-18

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/04 ,  H03H3/10 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H01L41/187 ,  H01L41/47 ,  H01L41/332 ,  H01L41/337 ,  H03H9/64

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US11373898B2

公开(公告)日：2022-06-28

申请号：US16969350

申请日：2019-02-12

Applicant: Soitec

Inventor： Daniel Delprat ,  Damien Parissi ,  Marcel Broekaart

IPC: H01L21/46 ,  H01L23/58 ,  H01L21/762 ,  H01L21/02 ,  H01L21/677

Abstract: A method for manufacturing a semiconductor on insulator type structure by transfer of a layer from a donor substrate onto a receiver substrate, comprises: a) the supply of the donor substrate and the receiver substrate, b) the formation in the donor substrate of an embrittlement zone delimiting the layer to transfer, c) the bonding of the donor substrate on the receiver substrate, the surface of the donor substrate opposite to the embrittlement zone with respect to the layer to transfer being at the bonding interface, and d) the detachment of the donor substrate along the embrittlement zone. A step of controlled modification of the curvature of the donor substrate and/or the receiver substrate is performed before the bonding step.

公开(公告)号：US11205702B2

公开(公告)日：2021-12-21

申请号：US16086275

申请日：2017-03-31

Applicant: Soitec

Inventor： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

IPC: H01L29/161 ,  H01L23/00 ,  H01L21/306

Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

公开(公告)号：US10826459B2

公开(公告)日：2020-11-03

申请号：US15735477

申请日：2016-06-09

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/10 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H01L41/47 ,  H03H3/04 ,  H01L41/332 ,  H01L41/337 ,  H03H9/64

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.