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公开(公告)号:US20190304891A1
公开(公告)日:2019-10-03
申请号:US16365063
申请日:2019-03-26
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Romain COFFY
IPC: H01L23/498 , H01L21/50 , H01L23/10 , H01L23/31 , H01L23/00 , H01L31/0203
Abstract: A cover for an electronic device includes a support body having a through-passage. An optical element which allows light to pass is mounted on said support body in a position extending across the through-passage. A surface of the optical element includes an electrically-conducting track configured as a security detection element. At least two electrical connection leads are rigidly attached to the support body and include first uncovered portions internal to the support body and electrically connected to spaced apart locations on the electrically-conducting track. The at least two electrical connection leads further including second uncovered portions external to said support body. The cover is mounted on a support plate carrying an electronic chip situated in the through-passage at a distance from the optical element.
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公开(公告)号:US20190189860A1
公开(公告)日:2019-06-20
申请号:US16218944
申请日:2018-12-13
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor: Jean-Michel RIVIERE , Romain COFFY , Karine SAXOD
IPC: H01L33/48 , H05K5/03 , H01L31/18 , H01L31/12 , H01L31/0232 , H01L31/0203 , H01L33/00 , H01L33/58
CPC classification number: H01L33/483 , H01L31/0203 , H01L31/02327 , H01L31/12 , H01L31/162 , H01L31/18 , H01L33/005 , H01L33/58 , H05K5/03
Abstract: An electronic circuit including a cover crossed by an element and having a planar main inner surface.
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公开(公告)号:US20240087977A1
公开(公告)日:2024-03-14
申请号:US18244534
申请日:2023-09-11
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Romain COFFY , Jerome LOPEZ
IPC: H01L23/367 , H01L23/00 , H01L23/373 , H01L23/498
CPC classification number: H01L23/3672 , H01L23/3735 , H01L23/49816 , H01L24/16 , H01L24/32 , H01L2224/16055 , H01L2224/16225 , H01L2224/32225 , H01L2924/18161 , H01L2924/351
Abstract: An integrated circuit includes an electronic chip having a face covered with a thermal interface material layer. A heat sink includes a mounting area fixed to the chip via the thermal interface material layer. The heat sink includes open notches extending into the mounting area to delimit fins separated from each other by the open notches.
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公开(公告)号:US20240047407A1
公开(公告)日:2024-02-08
申请号:US18228898
申请日:2023-08-01
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Younes BOUTALEB , Julien CUZZOCREA , Romain COFFY
IPC: H01L23/00
CPC classification number: H01L24/30 , H01L24/29 , H01L24/27 , H01L24/94 , H01L24/32 , H01L24/73 , H01L2224/73265 , H01L24/48 , H01L2224/48221 , H01L2224/48091 , H01L2224/94 , H01L2224/27848 , H01L2224/27416 , H01L2224/2761 , H01L2224/29012 , H01L2224/29011 , H01L2224/32221 , H01L2224/30051 , H01L2224/3003 , H01L2224/30505
Abstract: An integrated circuit package includes at least one electronic chip having a first face fastened onto a first face of a carrier substrate by an adhesive interface. The adhesive interface includes a crown formed of a first adhesive material that is fastened on the periphery of the first face of the electronic chip. The crown defining an internal housing. A second adhesive material, different than the first material, is deposited in the internal housing.
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公开(公告)号:US20240038644A1
公开(公告)日:2024-02-01
申请号:US18377962
申请日:2023-10-09
Applicant: STMicroelectronics (Grenoble 2)SAS
Inventor: Romain COFFY , Fabien QUERCIA
IPC: H01L23/498 , H01L21/48 , H01L23/552 , H01L23/66 , H01L23/00 , H01Q1/22
CPC classification number: H01L23/49811 , H01L21/4817 , H01L21/4853 , H01L23/552 , H01L23/66 , H01L24/48 , H01Q1/2283 , H01L2223/6677 , H01L2224/48227
Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
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公开(公告)号:US20230318165A1
公开(公告)日:2023-10-05
申请号:US18119026
申请日:2023-03-08
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Romain COFFY , Ouafa HAJJI , Asma HAJJI , Fabien QUERCIA
IPC: H01Q1/22 , H01L23/58 , H01L23/544 , H01L21/56 , H01Q1/48
CPC classification number: H01Q1/2283 , H01L21/56 , H01L23/544 , H01L23/585 , H01Q1/48 , H01L24/16 , H01L2223/54426
Abstract: An electronic device includes an electronic integrated circuit chip assembled on a first region of a substrate. A radiation element of an antenna is mounted to the substrate in a manner where it is separated from the substrate by a second layer of a second dielectric material, and i\s further offset with respect to the first region of the substrate so that the radiation element does not cover the electronic integrated circuit chip. A first coating layer of a first coating material covers at least a surface of the electronic integrated circuit chip facing away from the substrate further covers a surface of the radiation element facing away from the substrate.
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公开(公告)号:US20230266441A1
公开(公告)日:2023-08-24
申请号:US18112087
申请日:2023-02-21
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Romain COFFY , Younes BOUTALEB
CPC classification number: G01S7/4813 , H01L25/167 , H01L25/165
Abstract: A time-of-flight sensor includes a first light ray generation circuit and a second light ray reception circuit. A resin layer encapsulates the first light ray generation circuit and the second light ray reception circuit. A first region configured to emit light rays of the first light ray generation circuit is exposed at a surface of the resin layer. A second region configured to receive light rays of the second light ray reception circuit is also exposed at that surface of the resin layer. The surface of the resin layer is configured to be directed towards a scene.
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公开(公告)号:US20230245984A1
公开(公告)日:2023-08-03
申请号:US18128044
申请日:2023-03-29
Inventor: Denis FARISON , Romain COFFY , Jean-Michel RIVIERE
IPC: H01L23/00 , H01L21/56 , H01L23/528 , H01L25/065
CPC classification number: H01L23/576 , H01L21/563 , H01L23/528 , H01L24/09 , H01L24/32 , H01L24/48 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/4824 , H01L2224/49112 , H01L2225/06555 , H01L2924/14 , H04L9/002
Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
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公开(公告)号:US20210366865A1
公开(公告)日:2021-11-25
申请号:US17396346
申请日:2021-08-06
Inventor: Romain COFFY , Patrick LAURENT , Laurent SCHWARTZ
Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.
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公开(公告)号:US20210066554A1
公开(公告)日:2021-03-04
申请号:US17006128
申请日:2020-08-28
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Romain COFFY , Remi BRECHIGNAC , Jean-Michel RIVIERE
IPC: H01L33/52 , H01L33/44 , H01L33/62 , H01L31/0216 , H01L31/0203
Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.
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