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    Adaptive low power common mode buffer
    11.
    发明授权
    Adaptive low power common mode buffer 有权

    公开(公告)号：US11509323B2

    公开(公告)日：2022-11-22

    申请号：US17245592

    申请日：2021-04-30

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar ,  Ramji Gupta

    IPC: H03M1/12

    Abstract: A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.

    Dual gate FD-SOI transistor
    12.
    发明授权
    Dual gate FD-SOI transistor 有权

    公开(公告)号：US10134894B2

    公开(公告)日：2018-11-20

    申请号：US14985264

    申请日：2015-12-30

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Anand Kumar ,  Ankit Agrawal

    IPC: H01L29/78 ,  H01L21/265 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/786

    Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

    LOCKED LOOP CIRCUIT WITH REFERENCE SIGNAL PROVIDED BY UN-TRIMMED OSCILLATOR
    13.
    发明申请
    LOCKED LOOP CIRCUIT WITH REFERENCE SIGNAL PROVIDED BY UN-TRIMMED OSCILLATOR 审中-公开

    公开(公告)号：US20180287617A1

    公开(公告)日：2018-10-04

    申请号：US15475274

    申请日：2017-03-31

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar ,  Nitin Gupta ,  Nitin Jain

    IPC: H03L1/00 ,  H03L7/099 ,  H03L7/183

    Abstract: An electronic device disclosed herein includes a locked loop circuit configured to receive a reference signal intended to have an intended frequency, wherein the locked look circuit is intended to generate an intended output signal having an intended frequency equal to the intended frequency multiplied by an intended multiplier. A frequency counter counts a number of pulses of the reference signal during a time window so as to determine an actual frequency of the reference signal. A control circuit determines an actual multiplier for the locked loop circuit that, when multiplied by the actual frequency of the reference signal, causes the locked loop circuit to generate an actual output signal having an actual frequency equal to the intended frequency.

    SPREAD SPECTRUM CLOCK GENERATOR
    14.
    发明申请
    SPREAD SPECTRUM CLOCK GENERATOR 审中-公开

    公开(公告)号：US20180159544A1

    公开(公告)日：2018-06-07

    申请号：US15888153

    申请日：2018-02-05

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar ,  Gagan Midha

    IPC: H03L7/093 ,  H03L7/197 ,  H03L7/089 ,  H03L7/099

    CPC classification number: H03L7/093 ,  H03C3/095 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/1976 ,  H04B15/04

    Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.

    DUAL GATE FD-SOI TRANSISTOR
    15.
    发明申请
    DUAL GATE FD-SOI TRANSISTOR 审中-公开
    双门FD-SOI晶体管

    公开(公告)号：US20150129967A1

    公开(公告)日：2015-05-14

    申请号：US14231459

    申请日：2014-03-31

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar ,  Ankit Agrawal

    IPC: H01L27/12 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/266 ,  H01L27/092 ,  H01L21/84

    CPC classification number: H01L29/7831 ,  H01L21/26513 ,  H01L21/31111 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/78648

    Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

    Abstract translation: 具有双栅极场效应晶体管的电路模块设计采用完全耗尽的绝缘体上硅（FD-SOI）技术实现。 降低晶体管的阈值电压可以通过动态辅助栅极控制来实现，其中使用反向偏置技术来操作具有增强的开关性能的双栅极FD-SOI晶体管。 因此，这样的晶体管可以以低至约0.4V的非常低的核心电压供应电平工作，这允许晶体管快速响应并以更高的速度切换。 在逆变器，放大器，电平转换器和电压检测电路模块的电路仿真中示出了性能改进。

    Low power crystal oscillator
    17.
    发明授权
    Low power crystal oscillator 有权

    公开(公告)号：US11082006B2

    公开(公告)日：2021-08-03

    申请号：US16703250

    申请日：2019-12-04

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar ,  Nitin Jain

    IPC: H03B5/36 ,  H03B5/06

    Abstract: A clock signal is generated with an oscillator. A crystal oscillator core within the oscillator circuit is switched on to produce first and second oscillation signals that are approximately opposite in phase. When a difference between a voltage of the first oscillation signal and a voltage of the second oscillation signal exceeds an upper threshold range, the crystal oscillator core is switched off. When the difference between the voltage of the first oscillation signal and the voltage of the second oscillation signal falls below the upper threshold range, the crystal oscillator core is switched back on. This operation is repeated so as to produce the clock signal.

    Spread spectrum clock generator
    18.
    发明授权
    Spread spectrum clock generator 有权

    公开(公告)号：US09923566B1

    公开(公告)日：2018-03-20

    申请号：US15251065

    申请日：2016-08-30

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar ,  Gagan Midha

    IPC: H03L7/093 ,  H03L7/099 ,  H03L7/089 ,  H03L7/197

    CPC classification number: H03L7/093 ,  H03C3/095 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/1976 ,  H04B1/69

    Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.

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