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公开(公告)号：US20140320218A1
公开(公告)日：2014-10-30
申请号：US14261283
申请日：2014-04-24
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco Ippolito , Mario Chiricosta
IPC: H03L7/00
Abstract: A calibration circuit for a DCO includes a signal-conditioning module configured for (i) receiving at input an oscillating signal generated by the DCO and a reference signal, both designed to oscillate between a high logic value (“1”) and a low logic value (“0”), and (ii) detecting a respective first and second stable logic value of the reference signal and of the oscillating signal; and a period-to-voltage converter module coupled to the signal-conditioning module and configured for (iii) generating a difference signal identifying a difference between the period of the reference signal and the period of the oscillating signal, and (iv) controlling, on the basis of the difference signal, the DCO so as to conform the duration of the period of the oscillating signal to the duration of the period of the reference signal. Likewise described is a calibration method implemented by the calibration circuit.
Abstract translation: 用于DCO的校准电路包括信号调节模块，其被配置用于（i）在输入端接收由DCO产生的振荡信号和参考信号，两者被设计为在高逻辑值（“1”）和低逻辑 值（“0”），和（ii）检测参考信号和振荡信号的相应的第一和第二稳定逻辑值; 以及周期电压转换器模块，其耦合到所述信号调节模块并且被配置用于（iii）产生识别所述参考信号的周期与所述振荡信号的周期之间的差的差信号，以及（iv） 基于差分信号，DCO使得将振荡信号的周期的持续时间与参考信号的周期的持续时间相一致。 同样描述了由校准电路实现的校准方法。
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公开(公告)号：US11652458B2
公开(公告)日：2023-05-16
申请号：US17372262
申请日：2021-07-09
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco Ippolito , Michele Vaiana , Angelo Recchia
CPC classification number: H03F3/45183 , G05F3/245 , G06G7/186 , H03B5/24 , H03F3/393 , H03F3/4565 , H03F3/45475 , H03F3/45654 , H03F3/45753 , H03F2200/171
Abstract: A thermally-isolated-metal-oxide-semiconducting (TMOS) sensor has inputs coupled to first and second nodes to receive first and second bias currents, and an output coupled to a third node. A tail has a first conduction terminal coupled to the third node and a second conduction terminal coupled to a reference voltage. A control circuit applies a control signal to a control terminal of the tail transistor based upon voltages at the first and second nodes so that a common mode voltage at the first and second nodes is equal to a reference common mode voltage. A differential current integrator has a first input terminal coupled to the second node and a second input terminal coupled to the first node, and provides an output voltage indicative of an integral of a difference between a first output current at the first input terminal and a second output current at the second input terminal.
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公开(公告)号：US11368165B2
公开(公告)日：2022-06-21
申请号：US17211355
申请日：2021-03-24
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco Ippolito , Michele Vaiana
Abstract: A converter circuit includes an analog-to-digital signal conversion path. An input port receives an analog input signal having an offset, and an output port delivers a digital output signal quantized over M levels. The digital output signal is sensed by a digital-to-analog feedback path, which includes a digital-to-analog converter applying to the input port an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first and second states. M-bit digital word generation circuitry coupled to the digital-to-analog converter and sensitive to the two-state signal produces, alternately, during the first states, a first M-bit digital word, which is a function of the digital output signal quantized over M levels, and, during the second states, a second M-bit digital word, which is a function a correction value of the offset in the analog input signal.
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公开(公告)号：US20210336593A1
公开(公告)日：2021-10-28
申请号：US17372262
申请日：2021-07-09
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco Ippolito , Michele Vaiana , Angelo Recchia
Abstract: A thermally-isolated-metal-oxide-semiconducting (TMOS) sensor has inputs coupled to first and second nodes to receive first and second bias currents, and an output coupled to a third node. A tail has a first conduction terminal coupled to the third node and a second conduction terminal coupled to a reference voltage. A control circuit applies a control signal to a control terminal of the tail transistor based upon voltages at the first and second nodes so that a common mode voltage at the first and second nodes is equal to a reference common mode voltage. A differential current integrator has a first input terminal coupled to the second node and a second input terminal coupled to the first node, and provides an output voltage indicative of an integral of a difference between a first output current at the first input terminal and a second output current at the second input terminal.
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公开(公告)号：US11095261B2
公开(公告)日：2021-08-17
申请号：US16781493
申请日：2020-02-04
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco Ippolito , Michele Vaiana , Angelo Recchia
Abstract: An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.
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Patent Agency Ranking
公开(公告)号：US20200050305A1
公开(公告)日：2020-02-13
申请号：US16523302
申请日：2019-07-26
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco Ippolito , Angelo Recchia , Antonio Cicero , Pierpaolo Lombardo , Michele Vaiana
Abstract: A touchscreen resistive sensor includes a network of resistive sensor branches coupled to a number of sensor nodes arranged at touch locations of the touchscreen. A test sequence is performed by sequentially applying to each sensor node a reference voltage level, jointly coupling to a common line the other nodes, sensing a voltage value at the common line, and declaring a short circuit condition as a result of the voltage value sensed at the common line reaching a short circuit threshold. A current value level flowing at the sensor node to which the reference voltage level is applied is sensed and a malfunction of the resistive sensor branch coupled with the sensor node to which a reference voltage level is applied is generated as a result of the current value sensed at the sensor node reaching an upper threshold or lower threshold.
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公开(公告)号：US20180212514A1
公开(公告)日：2018-07-26
申请号：US15797643
申请日：2017-10-30
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco Ippolito
IPC: H02M3/07
CPC classification number: H02M3/07 , H02M1/15 , H02M2001/0003 , H02M2001/0045
Abstract: An embodiment circuit includes a charge pump configured to receive an input voltage at an input terminal, and a clock signal at a clock input, the charge pump being further configured to produce a first output voltage that is a multiple of the input voltage by a factor N. The circuit further includes an input stage including a reference terminal configured to receive a reference voltage, and an output terminal configured to provide the input voltage to the charge pump. The circuit also includes a capacitive element coupled to the charge pump and chargeable to a second output voltage, and a feedback network including a first feedback loop configured to feed back the first output voltage to an input of the input stage, and a second feedback loop configured to maintain a fixed offset between the first output voltage and the second output voltage.
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公开(公告)号：US10019026B2
公开(公告)日：2018-07-10
申请号：US14996684
申请日：2016-01-15
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco Ippolito , Mario Chiricosta
Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference, the circuit module including a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.
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公开(公告)号：US11740136B2
公开(公告)日：2023-08-29
申请号：US17011723
申请日：2020-09-03
Applicant: STMicroelectronics S.r.l.
Inventor： Michele Vaiana , Paolo Pesenti , Mario Chiricosta , Calogero Marco Ippolito , Mario Maiore
IPC: G01K3/14 , H03H17/02 , G01K7/02 , H03M3/00 , H03K19/003 , H03K19/018
CPC classification number: G01K3/14 , G01K7/02 , G01K7/021 , H03H17/02 , G01K2219/00 , H03K19/00307 , H03K19/01825 , H03M3/43 , H03M3/456 , H03M3/458
Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.
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公开(公告)号：US11275100B2
公开(公告)日：2022-03-15
申请号：US16781598
申请日：2020-02-04
Applicant: STMicroelectronics S.r.l.
Inventor： Michele Vaiana , Calogero Marco Ippolito , Angelo Recchia , Antonio Cicero , Pierpaolo Lombardo
Abstract: An amplification interface includes an input terminal receiving a sensor current and an output terminal supplying an output voltage. An analog integrator is connected to the input terminal and supplies the output voltage. A current generator is connected to the input of the analog integrator and generates a compensation current based on a drive signal. A control circuit generates the drive signal for the current generator based on a control signal representing an offset in the sensor current supplied by the sensor. The current generator generates, based on the driving signal, a positive or negative current. The control circuit determines a first duration and a second duration as a function of the control signal representing the offset in the sensor current, during the measurement interval, and sets the driving signal to a first logic value for the first duration and to a second logic value for the second duration.
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