公开(公告)号：US11929259B2

公开(公告)日：2024-03-12

申请号：US17353684

申请日：2021-06-21

Applicant: STMICROELECTRONICS, INC.

Inventor： Ian Harvey Arellano ,  Aaron Cadag ,  Ela Mia Cadag

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L21/4821 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L21/561 ,  H01L21/565 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.

公开(公告)号：US11916090B2

公开(公告)日：2024-02-27

申请号：US17342765

申请日：2021-06-09

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Rohn Kenneth Serapio ,  Ela Mia Cadag

IPC: H01L31/0203 ,  H01L27/146 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/49503 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16258 ,  H01L2224/8184

Abstract: A first side of a tapeless leadframe package is etched to form a ring shaped protrusion and a lead protrusion extending from a base layer. An integrated circuit die is mounted to tapeless leadframe package in flip chip orientation with a front side facing the first side. An electrical and mechanical attachment is made between a bonding pad of the integrated circuit die and the lead protrusion. A mechanical attachment is made between the front side of the integrated circuit die and the ring shaped protrusion. The integrated circuit die and the protrusions from the tapeless leadframe package are encapsulated within an encapsulating block. The second side of the tapeless leadframe package is then etched to remove portions of the base layer and define a lead for a leadframe from the lead protrusion and further define a die support for the leadframe from the ring shaped protrusion.

公开(公告)号：US11069601B2

公开(公告)日：2021-07-20

申请号：US16264822

申请日：2019-02-01

Applicant: STMicroelectronics, Inc.

Inventor： Ian Harvey Arellano ,  Aaron Cadag ,  Ela Mia Cadag

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.

公开(公告)号：US10529672B2

公开(公告)日：2020-01-07

申请号：US15693277

申请日：2017-08-31

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Lester Joseph Belalo ,  Ela Mia Cadag

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/78

Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame. This differential in height reduces the span of wires used to form electrical connections within the semiconductor package. These reductions in the span of the wires reduces the chances of wire to wire and wire to die short circuiting because the wire sweep of the wires is reduced when the molding compound is placed.

公开(公告)号：US10109563B2

公开(公告)日：2018-10-23

申请号：US15399234

申请日：2017-01-05

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Jefferson Talledo ,  Moonlord Manalo ,  Ela Mia Cadag ,  Rammil Seguido

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US20160293523A1

公开(公告)日：2016-10-06

申请号：US14674069

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Talledo ,  Ela Mia Cadag

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49555 ,  H01L23/49562 ,  H01L2224/37599 ,  H01L2224/40 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: An integrated circuit (IC) device may include a leadframe and an IC die having a first surface coupled to the lead frame and a second surface opposite the first surface. The IC device may further include a conductive clip including a first portion coupled to the second surface of the IC die, a second portion coupled to the first portion and extending laterally away from the IC die, and at least one flexible lead coupled to the second portion and looping back under the second portion toward the leadframe. Furthermore, a package may be over the leadframe, IC die, and conductive clip and have an opening therein exposing the at least one flexible lead.

Abstract translation: 集成电路（IC）装置可以包括引线框架和具有耦合到引线框架的第一表面和与第一表面相对的第二表面的IC管芯。 IC器件还可以包括导电夹子，该导电夹子包括耦合到IC芯片的第二表面的第一部分，耦合到第一部分并且横向远离IC芯片延伸的第二部分，以及耦合到第二部分的至少一个柔性引线 并且在第二部分之下环绕回引线框架。 此外，封装可以在引线框架，IC管芯和导电夹子之上，并且在其中具有露出至少一个柔性引线的开口。

公开(公告)号：US09324643B1

公开(公告)日：2016-04-26

申请号：US14566826

申请日：2014-12-11

Applicant: STMICROELECTRONICS, INC.

Inventor： Ela Mia Cadag ,  Ricky Calustre

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49541 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/544 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/0665

Abstract: An integrated circuit (IC) device includes an IC die and encapsulation material surrounding the IC die. A first set of leads is coupled to the IC die and has first contact pads exposed on a bottom surface of the encapsulation material adjacent its periphery. A second set of leads is coupled to the IC die and has second contact pads exposed on the bottom surface of the encapsulation material adjacent its periphery. The second set of leads has internal ends extending laterally inwardly from respective ones of the second contact pads to define a die pad area supporting the IC die.

Abstract translation: 集成电路（IC）装置包括IC芯片和围绕IC芯片的封装材料。 第一组引线耦合到IC管芯，并且具有暴露在邻近其周边的封装材料的底表面上的第一接触焊盘。 第二组引线被耦合到IC管芯并且具有暴露在密封材料的底表面上的邻近其周边的第二接触焊盘。 第二组引线具有从相应的第二接触焊盘横向向内延伸的内部端部，以限定支撑IC管芯的管芯焊盘区域。

公开(公告)号：US12255076B2

公开(公告)日：2025-03-18

申请号：US18435915

申请日：2024-02-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Ian Harvey Arellano ,  Aaron Cadag ,  Ela Mia Cadag

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.

公开(公告)号：US12211774B2

公开(公告)日：2025-01-28

申请号：US16848635

申请日：2020-04-14

Applicant: STMICROELECTRONICS, INC.

Inventor： Ela Mia Cadag ,  Frederick Ray Gomez ,  Aaron Cadag

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Generally described, one or more embodiments are directed to semiconductor packages comprising a plurality of leads and methods of forming same. The plurality of leads include active leads that are electrically coupled to bond pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and inactive leads that are not electrically coupled to bond pads of the semiconductor die. The active leads have surfaces that are exposed at a lower surface of the semiconductor package and forms lands, while the inactive leads are not exposed at the lower surface of the package.

公开(公告)号：US11557548B2

公开(公告)日：2023-01-17

申请号：US17137262

申请日：2020-12-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Aaron Cadag ,  Lester Joseph Belalo ,  Ela Mia Cadag

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame. This differential in height reduces the span of wires used to form electrical connections within the semiconductor package. These reductions in the span of the wires reduces the chances of wire to wire and wire to die short circuiting because the wire sweep of the wires is reduced when the molding compound is placed.