公开(公告)号：US20230253352A1

公开(公告)日：2023-08-10

申请号：US18300157

申请日：2023-04-13

申请人： ROHM CO., LTD.

发明人： Takukazu OTSUKA

IPC分类号： H01L23/00 ,  H01L29/739 ,  H01L29/78 ,  H01L23/495 ,  H01L29/417 ,  H01L25/07 ,  H01L23/373 ,  H01L29/12 ,  H01L29/161 ,  H01L29/41

CPC分类号： H01L24/08 ,  H01L29/739 ,  H01L29/78 ,  H01L23/4952 ,  H01L29/417 ,  H01L25/072 ,  H01L23/49524 ,  H01L23/3735 ,  H01L29/12 ,  H01L24/03 ,  H01L24/48 ,  H01L24/85 ,  H01L29/161 ,  H01L29/41 ,  H01L2224/48091 ,  H01L2924/13055 ,  H01L2224/45124 ,  H01L2224/40 ,  H01L2224/45565 ,  H01L2224/45624 ,  H01L24/45 ,  H01L2224/45147 ,  H01L2224/08501 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/85205

摘要： A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device.

公开(公告)号：US10002837B2

公开(公告)日：2018-06-19

申请号：US15547583

申请日：2016-04-15

申请人： DENSO CORPORATION

发明人： Kenji Onoda ,  Syoichirou Oomae

IPC分类号： H01L29/49 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H02P27/06

CPC分类号： H01L23/562 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/4871 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/40 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/371 ,  H01L2224/37599 ,  H01L2224/40 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/83815 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14252 ,  H01L2924/181 ,  H01L2924/351 ,  H02P27/06 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： A semiconductor device includes a metal member, a first semiconductor chip, a second semiconductor chip, a first solder and a second solder. A quantity of heat generated in the first semiconductor chip is greater than the second semiconductor chip. The second semiconductor chip is formed of a material having larger Young's modulus than the first semiconductor chip. The first semiconductor chip has a first metal layer connected to the metal member through a first solder at a surface facing the metal member. The second semiconductor chip has a second metal layer connected to the metal member through a second solder at a surface facing the metal member. A thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder corresponding to a part of an outer peripheral edge of the second metal layer.

公开(公告)号：US09818675B2

公开(公告)日：2017-11-14

申请号：US14674069

申请日：2015-03-31

申请人： STMICROELECTRONICS, INC.

发明人： Jefferson Talledo ,  Ela Mia Cadag

IPC分类号： H01L23/495 ,  H01L23/31

CPC分类号： H01L23/49513 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49555 ,  H01L23/49562 ,  H01L2224/37599 ,  H01L2224/40 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/37099

摘要： An integrated circuit (IC) device may include a leadframe and an IC die having a first surface coupled to the lead frame and a second surface opposite the first surface. The IC device may further include a conductive clip including a first portion coupled to the second surface of the IC die, a second portion coupled to the first portion and extending laterally away from the IC die, and at least one flexible lead coupled to the second portion and looping back under the second portion toward the leadframe. Furthermore, a package may be over the leadframe, IC die, and conductive clip and have an opening therein exposing the at least one flexible lead.

公开(公告)号：US20170133294A1

公开(公告)日：2017-05-11

申请号：US15106804

申请日：2015-04-28

申请人： Shindengen Electric Manufacturing CO., Ltd.

发明人： Kosuke IKEDA

IPC分类号： H01L23/367 ,  H01L25/07 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L23/3675 ,  H01L21/4871 ,  H01L21/563 ,  H01L23/00 ,  H01L23/24 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3121 ,  H01L24/33 ,  H01L25/07 ,  H01L25/071 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/37599 ,  H01L2224/40 ,  H01L2924/00014 ,  H01L2224/37099

摘要： A semiconductor module (100) has a first insulating substrate (11); a first conductor layer (12) provided on a mounting surface of the first insulating substrate (11); a first electronic element (13) provided on the first conductor layer (12); a sealing resin (80), which covers an overall mounting region within the mounting surface of the first insulating substrate (11), the first conductor layer (12), and the first electronic element (13); and a frame body (70), which is made of metal and covers the overall sealing resin (80).

公开(公告)号：US20160336099A1

公开(公告)日：2016-11-17

申请号：US15110096

申请日：2015-01-07

申请人： MITSUBISHI MATERIALS CORPORATION

发明人： Toshiyuki Nagase ,  Hiroya Ishizuka

IPC分类号： H01C1/084 ,  H01C17/00 ,  H01C17/28 ,  H01C1/14

CPC分类号： H01C1/084 ,  H01C1/01 ,  H01C1/14 ,  H01C1/142 ,  H01C1/144 ,  H01C17/006 ,  H01C17/28 ,  H01C17/281 ,  H01C17/283 ,  H01L2224/40 ,  H01L2924/181 ,  H01L2924/00012

摘要： In this resistor, a heat sink (Al member) (23) and the other surface (11b) of a ceramic substrate (11) are joined together using an Al—Si-based brazing filler material. The Al—Si-based brazing filler material has a melting point in a range of approximately 600° C. to 700° C. When the heat sink (23) and the ceramic substrate (11) are joined together using the Al—Si-based brazing filler material, it is possible to prevent the derogation of the heat resistance and thermal deterioration during joining at the same time.

摘要翻译： 在该电阻器中，使用Al-Si系钎焊料将散热器（Al构件）（23）和陶瓷基板（11）的另一面（11b）接合在一起。 Al-Si系钎焊料的熔点为约600℃〜700℃。当散热器（23）和陶瓷基板（11）使用Al-Si- 可以同时防止接合时的耐热性和热劣化的减损。

公开(公告)号：US20110278655A1

公开(公告)日：2011-11-17

申请号：US13192584

申请日：2011-07-28

申请人： Takayuki Hashimoto ,  Noboru Akiyama ,  Masaki Shiraishi ,  Tetsuya Kawashima

发明人： Takayuki Hashimoto ,  Noboru Akiyama ,  Masaki Shiraishi ,  Tetsuya Kawashima

IPC分类号： H01L27/06

CPC分类号： H01L25/16 ,  G06F1/26 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/40 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.

摘要翻译： 降低了电源单元主电路的寄生电感。 在具有用于高侧开关的功率MOSFET和低侧开关的功率MOSFET串联的电路的非绝缘DC-DC转换器中，用于高侧开关的功率MOSFET和用于低侧开关的功率MOSFET是 由n沟道垂直MOSFET形成，并且用于高侧开关的功率MOSFET的源极和用于低侧开关的功率MOSFET的漏电极经由相同的管芯焊盘电连接。

公开(公告)号：US20100176430A1

公开(公告)日：2010-07-15

申请号：US12721201

申请日：2010-03-10

申请人： Takayuki Hashimoto ,  Noboru Akiyama ,  Masaki Shiraishi ,  Tetsuya Kawashima

发明人： Takayuki Hashimoto ,  Noboru Akiyama ,  Masaki Shiraishi ,  Tetsuya Kawashima

IPC分类号： H01L27/06

CPC分类号： H01L25/16 ,  G06F1/26 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/40 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are

摘要翻译： 本发明提供一种降低电源单元的主电路的寄生电感的技术。 在具有用于高侧开关的功率MOSFET和低侧开关的功率MOSFET串联的电路的非绝缘DC-DC转换器中，用于高侧开关的功率MOSFET和用于低侧开关的功率MOSFET是 由n沟道垂直MOSFET形成，用于高侧开关的功率MOSFET的源极和用于低边开关的功率MOSFET的漏电极

公开(公告)号：US20090189291A1

公开(公告)日：2009-07-30

申请号：US12019282

申请日：2008-01-24

申请人： Stefan Landau ,  Joachim Mahler ,  Thomas Wowra

发明人： Stefan Landau ,  Joachim Mahler ,  Thomas Wowra

IPC分类号： H01L21/50 ,  H01L23/48

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/19 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L25/074 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/40 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/838 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12032 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/3512

摘要： A multi-chip module and method is disclosed. One embodiment provides an electronic module having a first metal structure and a second metal structure. A first semiconductor chip is electrically connected with its back side to the first metal structure. A second semiconductor chip is arranged with its back side lying over the front side of the first semiconductor chip. The second metal structure includes multiple external contact elements attached over the front side of the second semiconductor chip. At least two of the multiple external contact elements are electrically connected to the front side of the second semiconductor chip.

摘要翻译： 公开了一种多芯片模块和方法。 一个实施例提供一种具有第一金属结构和第二金属结构的电子模块。 第一半导体芯片与其背面电连接到第一金属结构。 第二半导体芯片被布置成其后侧位于第一半导体芯片的前侧。 第二金属结构包括附接在第二半导体芯片的前侧上的多个外部接触元件。 多个外部接触元件中的至少两个电连接到第二半导体芯片的前侧。

公开(公告)号：US07253503B1

公开(公告)日：2007-08-07

申请号：US10986634

申请日：2004-11-12

申请人： James M. Fusaro ,  Robert F. Darveaux ,  Pablo Rodriguez

发明人： James M. Fusaro ,  Robert F. Darveaux ,  Pablo Rodriguez

IPC分类号： H01L23/495

CPC分类号： H01L23/66 ,  H01L23/3121 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/40 ,  H01L2224/45 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A planar metal die pad and planar metal are attached to the second surface of the polyimide sheet. The apertures in the polyimide sheet are juxtaposed to the leads. A package made using the substrate includes an integrated circuit device mounted above the first surface of the polyimide sheet opposite the die pad. Bond wires are connected between the integrated circuit device and the leads through the apertures in the polyimide sheet. An encapsulant material covers the first surface of the polyimide sheet, the integrated circuit device, the bone wires, and the apertures. The die pad and leads are exposed at an exterior surface of the package.

摘要翻译： 公开了用于制造封装的集成电路器件封装和衬底。 衬底的一个实施例包括具有第一表面，相对的第二表面以及第一和第二表面之间的孔的聚酰亚胺的平面片。 平面金属管芯焊盘和平面金属附接到聚酰亚胺片的第二表面。 聚酰亚胺片中的孔与引线并列。 使用该基板制成的封装包括集成电路装置，安装在与芯片衬垫相对的聚酰亚胺片的第一表面上方。 接合线通过聚酰亚胺片中的孔连接在集成电路器件和引线之间。 密封剂材料覆盖聚酰亚胺片的第一表面，集成电路器件，骨线和孔。 芯片焊盘和引线暴露在封装的外表面。

公开(公告)号：US20180115278A1

公开(公告)日：2018-04-26

申请号：US15793122

申请日：2017-10-25

申请人： Tyco Electronics (Shanghai) Co. Ltd. ,  Tyco Electronics Holdings (Bermuda) No. 7 Limited

发明人： Shih Ying ,  Yuan Zhong ,  Zhenhua Zhang

IPC分类号： H02S40/34 ,  H02G3/16 ,  H02G3/14 ,  H01R13/66 ,  H01R24/60 ,  H02G3/08

CPC分类号： H02S40/345 ,  H01L2224/40 ,  H01R13/6641 ,  H01R24/60 ,  H01R2107/00 ,  H02G3/081 ,  H02G3/14 ,  H02G3/16

摘要： A photovoltaic junction box comprises a box body, a plurality of conductive terminals, and at least one diode chip. The at least one diode chip is disposed in the box body.