公开(公告)号：US20160307899A1

公开(公告)日：2016-10-20

申请号：US15197509

申请日：2016-06-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US20150097212A1

公开(公告)日：2015-04-09

申请号：US14048232

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Pierre MORIN ,  Qing LIU ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/823807 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/7842

Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.

Abstract translation: 一种用于形成半导体器件的方法包括在应力半导体绝缘体晶片的应力半导体层上形成掩模层。 形成包围应力半导体层的隔离沟槽。 隔离沟槽延伸穿过掩模层并穿过SOI晶片的氧化物层。 绝缘体形成在隔离沟槽中。 在电介质体和应力半导体层的相邻侧壁上形成松弛减小衬垫。 应力半导体层上的掩模层被去除。

公开(公告)号：US20210057414A1

公开(公告)日：2021-02-25

申请号：US17093528

申请日：2020-11-09

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US20200161299A1

公开(公告)日：2020-05-21

申请号：US16751036

申请日：2020-01-23

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  Prasanna KHARE ,  Nicolas LOUBET

IPC: H01L27/088 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/225 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L21/84

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US20200020808A1

公开(公告)日：2020-01-16

申请号：US16584647

申请日：2019-09-26

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15 ,  H01L29/16 ,  H01L29/161

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US20180315666A1

公开(公告)日：2018-11-01

申请号：US16027707

申请日：2018-07-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN ,  Yann MIGNOT

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417 ,  H01L21/02 ,  H01L29/165 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20180069121A1

公开(公告)日：2018-03-08

申请号：US15798976

申请日：2017-10-31

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/15 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US20170053981A1

公开(公告)日：2017-02-23

申请号：US15345250

申请日：2016-11-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas LOUBET ,  Prasanna KHARE

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L27/088 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

Abstract translation: 通过在器件的制造期间在半导体沟道和衬底之间插入绝缘层来防止FinFET器件中的沟道到衬底泄漏。 类似地，通过在源极/漏极区域和衬底之间插入绝缘层来隔离源极/漏极区域来防止FinFET器件中的源极/漏极到衬底泄漏。 形成这样的绝缘层将物理和电气上的导电路径与衬底隔离，从而防止电流泄漏。 在由多层堆叠构成的半导体鳍片阵列中，去除底部材料，从而产生悬浮在硅表面上方的翅片阵列。 然后在剩余的顶部翅片材料下面形成的间隙填充氧化物以更好地支撑翅片并且将翅片阵列与基底隔离开。

公开(公告)号：US20170012127A1

公开(公告)日：2017-01-12

申请号：US15255862

申请日：2016-09-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

Abstract translation: 半导体器件可以包括衬底，在衬底上方具有沟道区域的鳍，以及与沟道区相邻的源区和漏区，以在沟道区上产生剪切和正应变。 半导体器件可以包括衬底，在衬底上方的鳍片，其中具有沟道区域，与沟道区域相邻的源极和漏极区域以及沟道区域上的栅极。 翅片可以相对于源极和漏极区域倾斜以在沟道区域上产生剪切和正常应变。

公开(公告)号：US20160190304A1

公开(公告)日：2016-06-30

申请号：US14588221

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pierre MORIN ,  Kangguo CHENG ,  Jody FRONHEISER ,  Xiuyu CAI ,  Juntao LI ,  Shogo MOCHIZUKI ,  Ruilong XIE ,  Hong HE ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7849

Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.

Abstract translation: 具有基本上无缺陷的SiGe应变松弛缓冲层的改性硅衬底适用于构建高性能CMOS FinFET器件的基础。 可以通过切割或分割应变的外延膜来形成基本上无缺陷的SiGe应变松弛缓冲层，使得薄膜段的边缘经历弹性应变弛豫。 当片段足够小时，整个膜被松弛，使得膜基本上没有位错缺陷。 一旦形成了基本上无缺陷的应变松弛缓冲层，则可以从松弛的SRB层外延生长应变通道层。 然后将应变通道层图案化以产生用于FinFET器件的鳍片。 在一个实施例中，形成双应变通道层 - 用于NFET器件的拉伸应变层，以及用于PFET器件的压缩应变层。