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公开(公告)号：US20230161486A1
公开(公告)日：2023-05-25
申请号：US18058613
申请日：2022-11-23
Applicant: STMicroelectronics (Grand Ouest)SAS
Inventor： Loic Pallardy , Michel Jaouen
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/0637 , G06F3/0673
Abstract: In accordance with an embodiment, a method for managing a memory within a system-on-a-chip including a processor, a memory and a firewall device, includes: generating, by the processor, a request to access the memory, where the request has a access permission level; controlling, by the firewall device, access to the at least one memory region of the memory as a function of the access permission level of the request and a respective access permission level associated with at least one memory region; and erasing, by the firewall device, the at least one memory regions when its respective access permission level is modified, where erasing comprises performing a hardware-implemented erasure.
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公开(公告)号：US20230161484A1
公开(公告)日：2023-05-25
申请号：US17989389
申请日：2022-11-17
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Loic Pallardy , Michel Jaouen
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/0655 , G06F3/0673
Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.
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公开(公告)号：US20220156217A1
公开(公告)日：2022-05-19
申请号：US17587954
申请日：2022-01-28
Inventor： Loic Pallardy , Nicolas Saux
IPC: G06F13/40 , G06F13/362
Abstract: A system including a first port configured to simultaneously couple with a first device and a second device; and a management circuit configured to route a data signal received from a first controller to the first device in response to receiving a first-device direction from the first controller and route the data signal received from the first controller to the second device in response to receiving a second-device direction from the first controller unless an override condition for the management circuit is satisfied.
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公开(公告)号：US20250053318A1
公开(公告)日：2025-02-13
申请号：US18932199
申请日：2024-10-30
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Loic Pallardy , Michel Jaouen
IPC: G06F3/06
Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.
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15.发明公开公开(公告)号：US20230291645A1
公开(公告)日：2023-09-14
申请号：US18321516
申请日：2023-05-22
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , H04L41/0803
CPC classification number: H04L41/0813 , H04L49/109 , G06F15/17306 , G06F15/177 , H04L41/0803 , G06F21/85
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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Patent Agency Ranking
公开(公告)号：US11614949B2
公开(公告)日：2023-03-28
申请号：US16899327
申请日：2020-06-11
Inventor： Loic Pallardy , Ignazio Antonino Urzi , Jean-Francis Duret
IPC: G06F13/40 , G06F9/4401 , G06F9/30 , G06F9/345 , G06F9/445
Abstract: An integrated circuit comprises a processing unit configured for booting up with a set of boot instructions, then for determining the size of the instructions of an application programme and potentially rebooting on its own initiative, while being reconfigured, in order for it to execute the instructions of the application program. Only one boot memory is needed as a consequence.
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公开(公告)号：US20230015027A1
公开(公告)日：2023-01-19
申请号：US17812883
申请日：2022-07-15
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Michel Jaouen , Loic Pallardy
IPC: G06F21/62 , G06F12/0802
Abstract: In an embodiment a method for managing access rights of software tasks executed by a processing unit (CPU) using a cache memory containing execution data of the tasks in memory locations, each execution data having an attribute representative of a level of access right of the respective task, includes changing the attributes of the locations of the cache memory when the access rights of at least one task changes and retaining the execution data contained in the locations of the cache memory.
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18.发明申请公开(公告)号：US20220179659A1
公开(公告)日：2022-06-09
申请号：US17540041
申请日：2021-12-01
Inventor： Loic Pallardy , Michael Soulie
IPC: G06F9/4401 , G06F13/40
Abstract: The method for resetting a master device, configured to initiate transactions on a bus of a system on a chip, includes monitoring a completed or not state of the transactions initiated by the master device. In the case of reception of a command to reset the master device, the method includes a transmission of an effective reset command to the master device when the transactions initiated by the master device are in the completed state.
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公开(公告)号：US20210160134A1
公开(公告)日：2021-05-27
申请号：US16951198
申请日：2020-11-18
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L12/24 , H04L12/933
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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20.发明公开公开(公告)号：US20230342279A1
公开(公告)日：2023-10-26
申请号：US18306032
申请日：2023-04-24
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Michel Jaouen , Loic Pallardy
CPC classification number: G06F11/3466 , G06F11/3612
Abstract: A method is provided for monitoring an execution of a selected program code portion stored in a memory address range between a start address and an end address. The method includes starting a timing when a program counter points to the start address of the selected program code portion. Current values of the program counter are compared with a set of target addresses specific to the selected program code portion including the end address of the selected program code portion. The timing is stopped when the program counter points to the end address of the selected program code portion. An error signal is generated in response to the timing duration being outside a nominal duration range specific to the selected program code portion.
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